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path: root/bsp/coreip-e20-arty
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2019-03-26Merge pull request #211 from sifive/reglistsCarsten Gosvig
Added design.reglist files to all bsp's based on screenlog output
2019-03-25Update header to include PLIC, CLIC SUBINTERRUPTSBunnaroath Sou
2019-03-21Update lds files to exclude itim in .text and PLIC subinterruptsBunnaroath Sou
2019-03-21Added design.reglist files to all bsp's based on screenlog outputcgsfv
2019-03-18Remove metal.lds which is now metal.default.ldsBunnaroath Sou
2019-03-18Add new linker target files for default, ramrodata, scratchpadBunnaroath Sou
2019-03-18Update Arty clock to reflects HWBunnaroath Sou
2019-03-14Fix typos and formatting in settings.mkNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-14Create TARGET_TAGSNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-07Update BSPsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-07Fix the metal,entry chosen node in the 2-series Arty targetsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-06Update/add E20, E21, E24 arty targets for all 19.2 CoreIPs releaseBunnaroath Sou