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path: root/bsp/coreip-e31-arty/design.dts
AgeCommit message (Collapse)Author
2019-06-19Delete coreip BSPsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-05-21Modify BSP DTSs to use riscv,pmpregions propertyNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-18Update Arty clock to reflects HWBunnaroath Sou
2019-03-05Update/add E31, E34, S51, S54 arty targets for all 19.2 CoreIPs releaseBunnaroath Sou
2019-02-11Update BSPs for hw-exec-breakpointBunnaroath Sou
2019-02-04Replace all mee with metalNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-30Add PMPs to coreip DTSsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-09Update DTS and freedom-mee to support interruptBunnaroath Sou
2019-01-03Add fixed-clocks to Arty boardsNathaniel Graff
The serial device needs a clock in the DTS to initialize. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-13Add MEE BSP for E31 CoreIP ArtyNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>