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path: root/bsp/coreip-e31-arty
AgeCommit message (Collapse)Author
2019-05-21Modify BSP DTSs to use riscv,pmpregions propertyNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-05-20Update BSP files to pickup inline supportBunnaroath Sou
2019-05-02Update BSPs for platform headerNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-04-30Update metal.*, *.dts and settings to latestBunnaroath Sou
2019-04-12Update BSPs for Unleashed and U54(MC)Nathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-26Making dhrystone publicBunnaroath Sou
2019-03-26Merge pull request #211 from sifive/reglistsCarsten Gosvig
Added design.reglist files to all bsp's based on screenlog output
2019-03-25Update header to include PLIC, CLIC SUBINTERRUPTSBunnaroath Sou
2019-03-21Update lds files to exclude itim in .text and PLIC subinterruptsBunnaroath Sou
2019-03-21Added design.reglist files to all bsp's based on screenlog outputcgsfv
2019-03-19Remove accidental added filesBunnaroath Sou
2019-03-18Remove metal.lds which is now metal.default.ldsBunnaroath Sou
2019-03-18Add new linker target files for default, ramrodata, scratchpadBunnaroath Sou
2019-03-18Update Arty clock to reflects HWBunnaroath Sou
2019-03-14Create TARGET_TAGSNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-07Update BSPsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-05Update/add E31, E34, S51, S54 arty targets for all 19.2 CoreIPs releaseBunnaroath Sou
2019-03-05Add RISCV_CMODEL to settings.mkNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-02-27Spellcheck correction readme for bsp targets for E20, E21, E31/Arty, S51/ArtyBunnaroath Sou
2019-02-26Add corrected formatting for bullet listsKevin Mills
Markdown bullet lists should: (1) have a blank line before and after the list; (2) start each list item at the beginning of the line (no leading white-space) The markdown processor in Freedom Studio enforces these standards and does not render correctly otherwise.
2019-02-25Adding readme to bsp targets for E20, E21, E31/Arty, S51/ArtyBunnaroath Sou
2019-02-14Update BSPsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-02-11Update BSPs for hw-exec-breakpointBunnaroath Sou
2019-02-04Regen BSPs for metal renameNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-02-04Replace all mee with metalNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-02-01Update BSP files and freedom-mee to reflect their latest updateBunnaroath Sou
2019-01-31Update BSP files after unit test e24 clic interruptsBunnaroath Sou
2019-01-30Update BSPs for PMPsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-30Add PMPs to coreip DTSsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-29Regen BSPs for separate stacks and heapsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-15Update mee.h files for freedom-metal clic supportBunnaroath Sou
2019-01-11Update freedom-mee and mee.h files to pickup interrupt fixesBunnaroath Sou
2019-01-09Update DTS and freedom-mee to support interruptBunnaroath Sou
2019-01-07Merge pull request #127 from sifive/itimNathaniel Graff
Add an ITIM example
2019-01-07Update BSPs for ITIMNathaniel Graff
2019-01-04Add OpenOCD configurations to Arty boardsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-03Update BSPs for Arty ClocksNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-03Add fixed-clocks to Arty boardsNathaniel Graff
The serial device needs a clock in the DTS to initialize. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-14Fix COREIP_HEX_WIDTHPalmer Dabbelt
I must have been too tired last night... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-13Add support for generating coreip hex files via elf2hexPalmer Dabbelt
This just calls elf2hex on the compiled elf files, producing a hex file that can be fed into RTL simulation. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-13Add MEE BSP for E31 CoreIP ArtyNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
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