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AgeCommit message (Collapse)Author
2019-01-31Update BSP files after unit test e24 clic interruptsBunnaroath Sou
2019-01-30Update BSPs for PMPsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-30Add PMPs to coreip DTSsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-29Regen BSPs for separate stacks and heapsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-15Update mee.h files for freedom-metal clic supportBunnaroath Sou
2019-01-11Update freedom-mee and mee.h files to pickup interrupt fixesBunnaroath Sou
2019-01-09Update DTS and freedom-mee to support interruptBunnaroath Sou
2019-01-07Merge pull request #127 from sifive/itimNathaniel Graff
Add an ITIM example
2019-01-07Update BSPs for ITIMNathaniel Graff
2019-01-04Add OpenOCD configurations to Arty boardsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-03Update BSPs for Arty ClocksNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-03Add fixed-clocks to Arty boardsNathaniel Graff
The serial device needs a clock in the DTS to initialize. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-14Fix COREIP_HEX_WIDTHPalmer Dabbelt
I must have been too tired last night... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-13Add support for generating coreip hex files via elf2hexPalmer Dabbelt
This just calls elf2hex on the compiled elf files, producing a hex file that can be fed into RTL simulation. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-13Add MEE BSP for E31 CoreIP ArtyNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
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