| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-01-03 | Add fixed-clocks to Arty boards | Nathaniel Graff | |
| The serial device needs a clock in the DTS to initialize. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> | |||
| 2018-12-14 | Fix COREIP_HEX_WIDTH | Palmer Dabbelt | |
| I must have been too tired last night... Signed-off-by: Palmer Dabbelt <palmer@sifive.com> | |||
| 2018-12-13 | Add support for generating coreip hex files via elf2hex | Palmer Dabbelt | |
| This just calls elf2hex on the compiled elf files, producing a hex file that can be fed into RTL simulation. Signed-off-by: Palmer Dabbelt <palmer@sifive.com> | |||
| 2018-12-13 | Add MEE BSP for E31 CoreIP Arty | Nathaniel Graff | |
| Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> | |||
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index : freedom-e-sdk | |
| my bad beginner RISC-V assembly LED blinking code. | silvan |
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