summaryrefslogtreecommitdiff
path: root/bsp/coreip-e31-rtl
AgeCommit message (Collapse)Author
2019-05-22Setup default options for dhrystone release.Hsiang-Chia.Huang
2019-05-20Update BSP files to pickup inline supportBunnaroath Sou
2019-05-02Update BSPs for platform headerNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-04-30Update metal.*, *.dts and settings to latestBunnaroath Sou
2019-04-12Update BSPs for Unleashed and U54(MC)Nathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-26Making dhrystone publicBunnaroath Sou
2019-03-26Merge pull request #211 from sifive/reglistsCarsten Gosvig
Added design.reglist files to all bsp's based on screenlog output
2019-03-25Update header to include PLIC, CLIC SUBINTERRUPTSBunnaroath Sou
2019-03-21Update lds files to exclude itim in .text and PLIC subinterruptsBunnaroath Sou
2019-03-21Added design.reglist files to all bsp's based on screenlog outputcgsfv
2019-03-18Make rtl target to use ram from dtim, flash from testramBunnaroath Sou
2019-03-18Remove metal.lds which is now metal.default.ldsBunnaroath Sou
2019-03-18Add new linker target files for default, ramrodata, scratchpadBunnaroath Sou
2019-03-18Update Arty clock to reflects HWBunnaroath Sou
2019-03-14Fix typos and formatting in settings.mkNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-14Create TARGET_TAGSNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-07Rename coreip-X to coreip-X-rtlNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-26 09:13:21 +0000