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path: root/bsp/coreip-e31-rtl
AgeCommit message (Expand)Author
2019-05-23Update BSPsNathaniel Graff
2019-05-22Update BSPsNathaniel Graff
2019-05-21Modify BSP DTSs to use riscv,pmpregions propertyNathaniel Graff
2019-05-20Update BSP files to pickup inline supportBunnaroath Sou
2019-05-02Update BSPs for platform headerNathaniel Graff
2019-04-30Update metal.*, *.dts and settings to latestBunnaroath Sou
2019-04-12Update BSPs for Unleashed and U54(MC)Nathaniel Graff
2019-03-26Making dhrystone publicBunnaroath Sou
2019-03-26Merge pull request #211 from sifive/reglistsCarsten Gosvig
2019-03-25Update header to include PLIC, CLIC SUBINTERRUPTSBunnaroath Sou
2019-03-21Update lds files to exclude itim in .text and PLIC subinterruptsBunnaroath Sou
2019-03-21Added design.reglist files to all bsp's based on screenlog outputcgsfv
2019-03-18Make rtl target to use ram from dtim, flash from testramBunnaroath Sou
2019-03-18Remove metal.lds which is now metal.default.ldsBunnaroath Sou
2019-03-18Add new linker target files for default, ramrodata, scratchpadBunnaroath Sou
2019-03-18Update Arty clock to reflects HWBunnaroath Sou
2019-03-14Fix typos and formatting in settings.mkNathaniel Graff
2019-03-14Create TARGET_TAGSNathaniel Graff
2019-03-07Rename coreip-X to coreip-X-rtlNathaniel Graff
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