| Age | Commit message (Collapse) | Author | |
|---|---|---|---|
| 2019-03-21 | Added design.reglist files to all bsp's based on screenlog output | cgsfv | |
| 2019-03-18 | Make rtl target to use ram from dtim, flash from testram | Bunnaroath Sou | |
| 2019-03-18 | Remove metal.lds which is now metal.default.lds | Bunnaroath Sou | |
| 2019-03-18 | Add new linker target files for default, ramrodata, scratchpad | Bunnaroath Sou | |
| 2019-03-18 | Update Arty clock to reflects HW | Bunnaroath Sou | |
| 2019-03-14 | Fix typos and formatting in settings.mk | Nathaniel Graff | |
| Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> | |||
| 2019-03-14 | Create TARGET_TAGS | Nathaniel Graff | |
| Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> | |||
| 2019-03-07 | Rename coreip-X to coreip-X-rtl | Nathaniel Graff | |
| Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com> | |||
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index : freedom-e-sdk | |
| my bad beginner RISC-V assembly LED blinking code. | silvan |
| summaryrefslogtreecommitdiff |