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2019-04-30Update metal.*, *.dts and settings to latestBunnaroath Sou
2019-04-30Add LEDs for HiFive1 boardsBunnaroath Sou
2019-04-12Update BSPs for Unleashed and U54(MC)Nathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-04-12Add Unleashed to targets in update-targets.shNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-04-12Fixup U54(MC) DTSNathaniel Graff
Add PMP nodes and the global-external-interrupts compat string Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-04-12Add target files for U54 and U54MCNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-04-12Fixup HiFive Unleashed design.dtsNathaniel Graff
- Add stdout-path - Add PMP node - Point tlclk at refclk instead of PRCI Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-04-12Add HiFive Unleashed board filesNathaniel Graff
Includes: - design.dts (including nodes for Vera board hardware) - openocd.cfg - settings.mk - README.md Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-04-11Add missing PMP nodesNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-31Enhance update-target script to also generate settings.mkBunnaroath Sou
2019-03-26Making dhrystone publicBunnaroath Sou
2019-03-26Merge pull request #211 from sifive/reglistsCarsten Gosvig
Added design.reglist files to all bsp's based on screenlog output
2019-03-25Merge pull request #214 from sifive/rc1-breakageBunnaroath Sou
Update header to include PLIC, CLIC SUBINTERRUPTS
2019-03-25Update header to include PLIC, CLIC SUBINTERRUPTSBunnaroath Sou
2019-03-25Add option to not run fixup-dts to update-targets.shNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-25Run scripts/fixup-dts from update-targets.shNathaniel Graff
2019-03-21Update lds files to exclude itim in .text and PLIC subinterruptsBunnaroath Sou
2019-03-21Added design.reglist files to all bsp's based on screenlog outputcgsfv
2019-03-19Remove accidental added filesBunnaroath Sou
2019-03-18Make rtl target to use ram from dtim, flash from testramBunnaroath Sou
2019-03-18Remove metal.lds which is now metal.default.ldsBunnaroath Sou
2019-03-18Add new linker target files for default, ramrodata, scratchpadBunnaroath Sou
2019-03-18Update Arty clock to reflects HWBunnaroath Sou
2019-03-18Add link target options to tools and envBunnaroath Sou
2019-03-14Remove SEGGER_JLINK_OB from settings.mkNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-14Fix typos and formatting in settings.mkNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-14Create TARGET_TAGSNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-07Rename coreip-X to coreip-X-rtlNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-07Merge pull request #195 from sifive/remove-legacyNathaniel Graff
Remove legacy BSPs and Software
2019-03-07Update BSPsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-07Fix the metal,entry chosen node in the 2-series Arty targetsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-07Remove legacy BSPNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-06Merge pull request #194 from sifive/arty-19.2Bunnaroath Sou
Add E76, S76 arty targets for all 19.2 CoreIPs release
2019-03-06Add E76, S76 arty targets for all 19.2 CoreIPs releaseBunnaroath Sou
2019-03-06Fix HiFive1 Rev B BSPNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-06Merge pull request #192 from sifive/arty-19.2Bunnaroath Sou
Update/add E20, E21, E24 arty targets for all 19.2 CoreIPs release
2019-03-06Update/add E20, E21, E24 arty targets for all 19.2 CoreIPs releaseBunnaroath Sou
2019-03-05Make update script independent of bashBunnaroath Sou
2019-03-05Merge pull request #190 from sifive/coreip-19.2Bunnaroath Sou
Update/add E31, E34, S51, S54 arty targets for all 19.2 CoreIPs release
2019-03-05Merge pull request #188 from sifive/hifive1-revbNathaniel Graff
Add HiFive1 RevB Support
2019-03-05Update/add E31, E34, S51, S54 arty targets for all 19.2 CoreIPs releaseBunnaroath Sou
2019-03-05Add codemodel settings for new targetsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-05Generate .hex for HiFive1 RevBNathaniel Graff
Set COREIP_MEM_WIDTH to cause the build system to generate a .hex file. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-05Generate BSP for HiFive1 RevBNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-05Add HiFive1 RevB to update-targets scriptNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-05Add HiFive1 Rev BNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-05Remove PMP reference from hifive1Nathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-05Add RISCV_CMODEL to settings.mkNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-01E76, S76 pmp not working, floating compiler/linker not workingBunnaroath Sou
2019-03-01Add CoreIPs E76, S76 for 19.2 relBunnaroath Sou
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