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2019-02-14Add clocking and pinmux to the SPI on hifive1Nathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-02-11Update BSPs for hw-exec-breakpointBunnaroath Sou
2019-02-11Minor cleanupBunnaroath Sou
2019-02-04Regen BSPs for metal renameNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-02-04Replace all mee with metalNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-02-01Merge pull request #168 from sifive/e24-artyBunnaroath Sou
E24 arty support
2019-02-01Update BSP files and freedom-mee to reflect their latest updateBunnaroath Sou
2019-01-31Merge pull request #166 from sifive/private-bspBunnaroath Sou
Update to generate bsp at a custom location
2019-01-31Update BSP files after unit test e24 clic interruptsBunnaroath Sou
2019-01-31Update dts, mee.h and mee.lds for E24 and clicBunnaroath Sou
2019-01-31Initual E24 support for GarbanzoBunnaroath Sou
2019-01-30Update to generate bsp at a custom locationBunnaroath Sou
2019-01-30Update BSPs for PMPsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-30Add PMPs to coreip DTSsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-29Regen BSPs for separate stacks and heapsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-15Update mee.h files for freedom-metal clic supportBunnaroath Sou
2019-01-11Update freedom-mee and mee.h files to pickup interrupt fixesBunnaroath Sou
2019-01-09Update DTS and freedom-mee to support interruptBunnaroath Sou
2019-01-07Update HiFive 1 to pull .itim sections into .textNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-07Merge pull request #127 from sifive/itimNathaniel Graff
Add an ITIM example
2019-01-07Update BSPs for ITIMNathaniel Graff
2019-01-04Fix BSP update script for MacOSNathaniel Graff
MacOS ls requires flags to appear before file arguments. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-04Add OpenOCD configurations to Arty boardsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-03HiFive 1 does not have an ITIMNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-03Update BSPs for Arty ClocksNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-03Add fixed-clocks to Arty boardsNathaniel Graff
The serial device needs a clock in the DTS to initialize. Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-17Merge pull request #119 from sifive/dt-tools-updaterPalmer Dabbelt
Add script for updating MEE BSPs
2018-12-14Add script for updating MEE BSPsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-14Fix COREIP_HEX_WIDTHPalmer Dabbelt
I must have been too tired last night... Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-13Add support for generating coreip hex files via elf2hexPalmer Dabbelt
This just calls elf2hex on the compiled elf files, producing a hex file that can be fed into RTL simulation. Signed-off-by: Palmer Dabbelt <palmer@sifive.com>
2018-12-13Add MEE BSP for S51 CoreIP ArtyNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-13Add MEE BSP for S51 CoreIPNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-13Add MEE BSP for E31 CoreIP ArtyNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-13Add MEE BSP for E31 CoreIPNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-13Add MEE BSP for Freedom E310 ArtyNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-13Add MEE BSP for SiFive HiFive1Nathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-12Merge pull request #76 from sifive/e300_arty_fixPalmer Dabbelt
E300 Arty: Don't specify the expected ID
2018-09-11fix for loopDrew Barbier
2018-08-08Include <encoding.h> so MSTATUS_FS is visible to start.SPalmer Dabbelt
2018-07-08support clint only projectsDrew Barbier
2018-07-08FS projectsDrew Barbier
2018-07-05support the E20Drew Barbier
2018-07-05fix level calculationDrew Barbier
2018-07-04clic driver level and priority functionsDrew Barbier
2018-07-02short msi handlerDrew Barbier
2018-07-02update descriptionDrew Barbier
2018-07-02accessors for other clic registersDrew Barbier
2018-07-02dont use pre-empt with buttonsDrew Barbier
2018-07-02e2 and clic startDrew Barbier
2018-06-29Add a CLIC interrupt examplePalmer Dabbelt
This example is fairly simple, but it does at least demonstrate how to use a C-based preemptable interrupt handler that's been registered in CLIC mode on a SiFive E21.
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