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path: root/bsp
AgeCommit message (Expand)Author
2019-06-06Submodule the freedom-devicetree-tools keep both in syncBunnaroath Sou
2019-06-02Add compile options for coremark and update freedom-metal repo.Hsiang-Chia.Huang
2019-05-31Run U54-MC on Hart 0Nathaniel Graff
2019-05-29Update BSP files to remove release labels until releaseBunnaroath Sou
2019-05-28Update BSPsNathaniel Graff
2019-05-23Update BSPsNathaniel Graff
2019-05-23Set the boot hart for u54mc to 1Nathaniel Graff
2019-05-22Update BSPsNathaniel Graff
2019-05-21Modify BSP DTSs to use riscv,pmpregions propertyNathaniel Graff
2019-05-20update-targets.sh warns on tool failureNathaniel Graff
2019-05-20Update BSP files to pickup inline supportBunnaroath Sou
2019-05-20Update metal to pick up inline supportBunnaroath Sou
2019-05-02Update BSPs for platform headerNathaniel Graff
2019-05-02Update Metal and build scripts for platform headerNathaniel Graff
2019-04-30Update metal.*, *.dts and settings to latestBunnaroath Sou
2019-04-30Add LEDs for HiFive1 boardsBunnaroath Sou
2019-04-12Update BSPs for Unleashed and U54(MC)Nathaniel Graff
2019-04-12Add Unleashed to targets in update-targets.shNathaniel Graff
2019-04-12Fixup U54(MC) DTSNathaniel Graff
2019-04-12Add target files for U54 and U54MCNathaniel Graff
2019-04-12Fixup HiFive Unleashed design.dtsNathaniel Graff
2019-04-12Add HiFive Unleashed board filesNathaniel Graff
2019-04-11Add missing PMP nodesNathaniel Graff
2019-03-31Enhance update-target script to also generate settings.mkBunnaroath Sou
2019-03-26Making dhrystone publicBunnaroath Sou
2019-03-26Merge pull request #211 from sifive/reglistsCarsten Gosvig
2019-03-25Merge pull request #214 from sifive/rc1-breakageBunnaroath Sou
2019-03-25Update header to include PLIC, CLIC SUBINTERRUPTSBunnaroath Sou
2019-03-25Add option to not run fixup-dts to update-targets.shNathaniel Graff
2019-03-25Run scripts/fixup-dts from update-targets.shNathaniel Graff
2019-03-21Update lds files to exclude itim in .text and PLIC subinterruptsBunnaroath Sou
2019-03-21Added design.reglist files to all bsp's based on screenlog outputcgsfv
2019-03-19Remove accidental added filesBunnaroath Sou
2019-03-18Make rtl target to use ram from dtim, flash from testramBunnaroath Sou
2019-03-18Remove metal.lds which is now metal.default.ldsBunnaroath Sou
2019-03-18Add new linker target files for default, ramrodata, scratchpadBunnaroath Sou
2019-03-18Update Arty clock to reflects HWBunnaroath Sou
2019-03-18Add link target options to tools and envBunnaroath Sou
2019-03-14Remove SEGGER_JLINK_OB from settings.mkNathaniel Graff
2019-03-14Fix typos and formatting in settings.mkNathaniel Graff
2019-03-14Create TARGET_TAGSNathaniel Graff
2019-03-07Rename coreip-X to coreip-X-rtlNathaniel Graff
2019-03-07Merge pull request #195 from sifive/remove-legacyNathaniel Graff
2019-03-07Update BSPsNathaniel Graff
2019-03-07Fix the metal,entry chosen node in the 2-series Arty targetsNathaniel Graff
2019-03-07Remove legacy BSPNathaniel Graff
2019-03-06Merge pull request #194 from sifive/arty-19.2Bunnaroath Sou
2019-03-06Add E76, S76 arty targets for all 19.2 CoreIPs releaseBunnaroath Sou
2019-03-06Fix HiFive1 Rev B BSPNathaniel Graff
2019-03-06Merge pull request #192 from sifive/arty-19.2Bunnaroath Sou
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