Age | Commit message (Collapse) | Author |
|
DTS Fixup bug fixes
|
|
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
|
|
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
|
|
Automatically add a 0x400000 byte offset to the entry point of FPGA and
Arty targets
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
|
|
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
|
|
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
|
|
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
|
|
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
|
|
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
|
|
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
|
|
|
|
The script is used as a holdover to add missing elements to design.dts
until the IP deliveries catch up with the set of information we need in
Freedom E SDK.
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
|