summaryrefslogtreecommitdiff
path: root/software
AgeCommit message (Collapse)Author
2019-04-11Update example-pmp to remove printf from exception handlerNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-26Making dhrystone publicBunnaroath Sou
2019-03-26Rename example-coreip-welcome to sifive-welcomeNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-26Update all software examples to use wildcards in makefileNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-15Add missing READMEs to software examplesNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-07Remove legacy examplesNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-03-06submodule updated and banner message updatedDavid Connelly
2019-03-05Updated to submoduleDavid Connelly
2019-03-05submodule name changeDavid Connelly
2019-03-05changed demo name to coreip-welcome to match bsp convention (was ↵David Connelly
coreplexip-welcome)
2019-03-04fix spacing, remove tabsDavid Connelly
2019-03-04coreplexip-welcome example updated using freedom metalDavid Connelly
2019-02-20Add empty example submoduleNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-02-14Add SPI example programNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-02-14Update minor fix to local-interrupt and its stacksizeBunnaroath Sou
2019-02-04Update examples for metal renameNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-30Add PMP example programNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-25Update Metal APINathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-14Simple RTL example returning pass and failBunnaroath Sou
2019-01-11Merge pull request #142 from sifive/ignore-hello-hexNathaniel Graff
Update hello example to ignore hello.hex
2019-01-11Add a simple local interrupt exampleBunnaroath Sou
2019-01-11Ignore and clean hello.hexNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-11Merge pull request #140 from sifive/itimNathaniel Graff
Update ITIM example to remove printfs
2019-01-10Update ITIM example to remove printfsNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2019-01-09Add timer interrupt exampleBunnaroath Sou
2019-01-09Add software interrupt exampleBunnaroath Sou
2019-01-07Add ITIM exampleNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-12-13Move hello example to submoduleNathaniel Graff
Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
2018-09-06HiFive-1 board bit-bang i2c demoHasan Unlu
Bit-bang i2c which is running around 400KHz. MPU6050 is used as an example device.
2018-07-09remove non-vectored exampleDrew Barbier
2018-07-05preemption support, csipid from button 2Drew Barbier
2018-07-05use new cspid instead of msipDrew Barbier
2018-07-05fix level calculationDrew Barbier
2018-07-04clic driver level and priority functionsDrew Barbier
2018-07-02short msi handlerDrew Barbier
2018-07-02update descriptionDrew Barbier
2018-07-02add busy wait and extra buttons/irqDrew Barbier
2018-07-02Delete clic_vectoredDrew Barbier
2018-07-02dont use pre-empt with buttonsDrew Barbier
2018-07-02e2 and clic startDrew Barbier
2018-06-29Add a CLIC interrupt examplePalmer Dabbelt
This example is fairly simple, but it does at least demonstrate how to use a C-based preemptable interrupt handler that's been registered in CLIC mode on a SiFive E21.
2018-01-26asm only programDrew Barbier
2017-11-17Speed up Dhrystone on the HiFive1Palmer Dabbelt
There's a handful of things that went wrong here: * The read-only data sections were mapped to flash, which is very slow. I just put them in the data segment, so they end up in the scratchpad. This is about a 10x hit, so it's really important. * The toolchain was an old version, which didn't have a fast memcpy implementation on 32-bit systems. This is about a 2x hit. * Some compiler flags were incorrect, including * -Os instead of -O3 * Missing -mexplicit-relocs * Missing -DNOENUM * Missing -falign-functions=4 I haven't checked how much those hurt With this, I get $ make software BOARD=freedom-e300-hifive1 PROGRAM=dhrystone LINK_TARGET=dhrystone $ make upload BOARD=freedom-e300-hifive1 PROGRAM=dhrystone LINK_TARGET=dhrystone Execution starts, 10000000 runs through Dhrystone Execution ends Final values of the variables used in the benchmark: Int_Glob: 5 should be: 5 Bool_Glob: 1 should be: 1 Ch_1_Glob: A should be: A Ch_2_Glob: B should be: B Arr_1_Glob[8]: 7 should be: 7 Arr_2_Glob[8][7]: 10000010 should be: Number_Of_Runs + 10 Ptr_Glob-> Ptr_Comp: -2147470264 should be: (implementation-dependent) Discr: 0 should be: 0 Enum_Comp: 2 should be: 2 Int_Comp: 17 should be: 17 Str_Comp: DHRYSTONE PROGRAM, SOME STRING should be: DHRYSTONE PROGRAM, SOME STRING Next_Ptr_Glob-> Ptr_Comp: -2147470264 should be: (implementation-dependent), same as above Discr: 0 should be: 0 Enum_Comp: 1 should be: 1 Int_Comp: 18 should be: 18 Str_Comp: DHRYSTONE PROGRAM, SOME STRING should be: DHRYSTONE PROGRAM, SOME STRING Int_1_Loc: 5 should be: 5 Int_2_Loc: 13 should be: 13 Int_3_Loc: 7 should be: 7 Enum_Loc: 1 should be: 1 Str_1_Loc: DHRYSTONE PROGRAM, 1'ST STRING should be: DHRYSTONE PROGRAM, 1'ST STRING Str_2_Loc: DHRYSTONE PROGRAM, 2'ND STRING should be: DHRYSTONE PROGRAM, 2'ND STRING Microseconds for one run through Dhrystone: 1.3 Dhrystones per Second: 714285.6 which is 1.55 DMIPS/MHz at 262 MHz. It's still a bit slower than our current stuff, but I don't remember what was actually in the HiFive1 so I'm not sure what we should be getting. I verified the clock is accurate with a stopwatch. I haven't bothered to go look through the binary, but I think we're about 10 cycles off so it should be managable.
2017-08-15blacklisted watchdog program for coreplexip-e51-arty boardGleb Gagarin
2017-08-10added ecall to vectored irq exampleDrew Barbier
2017-08-07HiFive1 AON Watchdog exampleDrew Barbier
2017-07-26changed synch trap entry to match other vectorsDrew Barbier
2017-07-26removed bin file commited by accidentDrew Barbier
2017-07-26fixed commentsDrew Barbier
2017-07-25added vectored interrupt exampleDrew Barbier
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-22 21:28:21 +0000