From f04c1a9df045903204d8018c71b2a028494bbac9 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Wed, 19 Dec 2018 15:15:32 -0800 Subject: Add fixed-clocks to Arty boards The serial device needs a clock in the DTS to initialize. Signed-off-by: Nathaniel Graff --- bsp/coreip-e31-arty/design.dts | 6 ++++++ bsp/coreip-s51-arty/design.dts | 6 ++++++ 2 files changed, 12 insertions(+) diff --git a/bsp/coreip-e31-arty/design.dts b/bsp/coreip-e31-arty/design.dts index 2e9eaff..fcefbb7 100644 --- a/bsp/coreip-e31-arty/design.dts +++ b/bsp/coreip-e31-arty/design.dts @@ -40,6 +40,11 @@ #size-cells = <1>; compatible = "SiFive,FE310G-soc", "fe310-soc", "sifive-soc", "simple-bus"; ranges; + hfclk: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32500000>; + }; L1: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L3 3 &L3 7>; @@ -105,6 +110,7 @@ interrupts = <5>; reg = <0x20000000 0x1000>; reg-names = "control"; + clocks = <&hfclk>; }; L12: spi@20004000 { compatible = "sifive,spi0"; diff --git a/bsp/coreip-s51-arty/design.dts b/bsp/coreip-s51-arty/design.dts index 23362f2..c0813ca 100644 --- a/bsp/coreip-s51-arty/design.dts +++ b/bsp/coreip-s51-arty/design.dts @@ -40,6 +40,11 @@ #size-cells = <1>; compatible = "SiFive,FE510G-soc", "fe510-soc", "sifive-soc", "simple-bus"; ranges; + hfclk: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32500000>; + }; L1: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L3 3 &L3 7>; @@ -105,6 +110,7 @@ interrupts = <5>; reg = <0x20000000 0x1000>; reg-names = "control"; + clocks = <&hfclk>; }; L12: spi@20004000 { compatible = "sifive,spi0"; -- cgit v1.2.3 From 6c499b707ad3864aa7f66805d6c9093813a80d3d Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Thu, 3 Jan 2019 09:28:33 -0800 Subject: Update BSPs for Arty Clocks Signed-off-by: Nathaniel Graff --- bsp/coreip-e31-arty/mee.h | 15 ++++++++++++++- bsp/coreip-s51-arty/mee.h | 15 ++++++++++++++- 2 files changed, 28 insertions(+), 2 deletions(-) diff --git a/bsp/coreip-e31-arty/mee.h b/bsp/coreip-e31-arty/mee.h index fe68d1f..9f89a75 100644 --- a/bsp/coreip-e31-arty/mee.h +++ b/bsp/coreip-e31-arty/mee.h @@ -1,7 +1,12 @@ #ifndef ASSEMBLY +#include #include #include #include +/* From clock@0 */ +asm (".weak __mee_dt_clock_0"); +struct __mee_driver_fixed_clock __mee_dt_clock_0; + /* From gpio@20002000 */ asm (".weak __mee_dt_gpio_20002000"); struct __mee_driver_sifive_gpio0 __mee_dt_gpio_20002000; @@ -14,6 +19,13 @@ struct __mee_driver_sifive_uart0 __mee_dt_serial_20000000; asm (".weak __mee_dt_teststatus_4000"); struct __mee_driver_sifive_test0 __mee_dt_teststatus_4000; +/* From clock@0 */ +struct __mee_driver_fixed_clock __mee_dt_clock_0 = { + .vtable = &__mee_driver_vtable_fixed_clock, + .clock.vtable = &__mee_driver_vtable_fixed_clock.clock, + .rate = 32500000UL, +}; + /* From gpio@20002000 */ struct __mee_driver_sifive_gpio0 __mee_dt_gpio_20002000 = { .vtable = &__mee_driver_vtable_sifive_gpio0, @@ -27,7 +39,8 @@ struct __mee_driver_sifive_uart0 __mee_dt_serial_20000000 = { .uart.vtable = &__mee_driver_vtable_sifive_uart0.uart, .control_base = 536870912UL, .control_size = 4096UL, - .clock = NULL, +/* From clock@0 */ + .clock = &__mee_dt_clock_0.clock, .pinmux = NULL, }; diff --git a/bsp/coreip-s51-arty/mee.h b/bsp/coreip-s51-arty/mee.h index fe68d1f..9f89a75 100644 --- a/bsp/coreip-s51-arty/mee.h +++ b/bsp/coreip-s51-arty/mee.h @@ -1,7 +1,12 @@ #ifndef ASSEMBLY +#include #include #include #include +/* From clock@0 */ +asm (".weak __mee_dt_clock_0"); +struct __mee_driver_fixed_clock __mee_dt_clock_0; + /* From gpio@20002000 */ asm (".weak __mee_dt_gpio_20002000"); struct __mee_driver_sifive_gpio0 __mee_dt_gpio_20002000; @@ -14,6 +19,13 @@ struct __mee_driver_sifive_uart0 __mee_dt_serial_20000000; asm (".weak __mee_dt_teststatus_4000"); struct __mee_driver_sifive_test0 __mee_dt_teststatus_4000; +/* From clock@0 */ +struct __mee_driver_fixed_clock __mee_dt_clock_0 = { + .vtable = &__mee_driver_vtable_fixed_clock, + .clock.vtable = &__mee_driver_vtable_fixed_clock.clock, + .rate = 32500000UL, +}; + /* From gpio@20002000 */ struct __mee_driver_sifive_gpio0 __mee_dt_gpio_20002000 = { .vtable = &__mee_driver_vtable_sifive_gpio0, @@ -27,7 +39,8 @@ struct __mee_driver_sifive_uart0 __mee_dt_serial_20000000 = { .uart.vtable = &__mee_driver_vtable_sifive_uart0.uart, .control_base = 536870912UL, .control_size = 4096UL, - .clock = NULL, +/* From clock@0 */ + .clock = &__mee_dt_clock_0.clock, .pinmux = NULL, }; -- cgit v1.2.3