From 4745766517d984d75b85d5497a9f2c68e8a39ce7 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Mon, 17 Dec 2018 16:25:19 -0800 Subject: HiFive 1 does not have an ITIM Signed-off-by: Nathaniel Graff --- bsp/sifive-hifive1/design.dts | 6 ------ 1 file changed, 6 deletions(-) diff --git a/bsp/sifive-hifive1/design.dts b/bsp/sifive-hifive1/design.dts index a71956a..26e4048 100644 --- a/bsp/sifive-hifive1/design.dts +++ b/bsp/sifive-hifive1/design.dts @@ -26,7 +26,6 @@ reg = <0>; riscv,isa = "rv32imac"; sifive,dtim = <&dtim>; - sifive,itim = <&itim>; status = "okay"; timebase-frequency = <1000000>; hlic: interrupt-controller { @@ -147,11 +146,6 @@ reg = <0x80000000 0x4000>; reg-names = "mem"; }; - itim: itim@8000000 { - compatible = "sifive,itim0"; - reg = <0x8000000 0x4000>; - reg-names = "mem"; - }; pwm@10015000 { compatible = "sifive,pwm0"; -- cgit v1.2.3 From 45ff0752939a1139c4e43379764753300b5c24f6 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Mon, 17 Dec 2018 16:27:13 -0800 Subject: Update to MEE with ITIM support Signed-off-by: Nathaniel Graff --- freedom-mee | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/freedom-mee b/freedom-mee index 22721b8..6a9b7f6 160000 --- a/freedom-mee +++ b/freedom-mee @@ -1 +1 @@ -Subproject commit 22721b8a89ac389d00753cc17d2a48af9bc1036f +Subproject commit 6a9b7f6fd421580fbd1b51219960b515c9d6a2e2 -- cgit v1.2.3 From c8611b1e729931796c0403023c755b694439853a Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 18 Dec 2018 13:15:24 -0800 Subject: Update BSPs for ITIM --- bsp/coreip-e31-arty/mee.lds | 27 +++++++++++++++++++++++++++ bsp/coreip-e31/mee.lds | 27 +++++++++++++++++++++++++++ bsp/coreip-s51-arty/mee.lds | 27 +++++++++++++++++++++++++++ bsp/coreip-s51/mee.lds | 27 +++++++++++++++++++++++++++ bsp/freedom-e310-arty/mee.lds | 27 +++++++++++++++++++++++++++ bsp/sifive-hifive1/mee.lds | 26 ++++++++++++++++++++++++++ 6 files changed, 161 insertions(+) diff --git a/bsp/coreip-e31-arty/mee.lds b/bsp/coreip-e31-arty/mee.lds index d0434f8..c081d9f 100644 --- a/bsp/coreip-e31-arty/mee.lds +++ b/bsp/coreip-e31-arty/mee.lds @@ -5,6 +5,7 @@ ENTRY(_enter) MEMORY { ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x10000 + itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000 flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 0x20000000 } @@ -12,7 +13,9 @@ PHDRS { flash PT_LOAD; ram_init PT_LOAD; + itim_init PT_LOAD; ram PT_NULL; + itim PT_NULL; } SECTIONS @@ -117,6 +120,30 @@ SECTIONS } >flash AT>flash :flash + .litimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_target_start = . ); + } >itim AT>flash :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>flash :itim_init + + + . = ALIGN(8); + PROVIDE( mee_segment_itim_target_end = . ); + + .lalign : { . = ALIGN(4); diff --git a/bsp/coreip-e31/mee.lds b/bsp/coreip-e31/mee.lds index c446555..538291d 100644 --- a/bsp/coreip-e31/mee.lds +++ b/bsp/coreip-e31/mee.lds @@ -4,6 +4,7 @@ ENTRY(_enter) MEMORY { + itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000 ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 0x8000000 } @@ -11,7 +12,9 @@ PHDRS { flash PT_LOAD; ram_init PT_LOAD; + itim_init PT_LOAD; ram PT_LOAD; + itim PT_LOAD; } SECTIONS @@ -116,6 +119,30 @@ SECTIONS } >ram AT>ram :ram + .litimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_source_start = . ); + } >ram AT>ram :ram + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_target_start = . ); + } >itim AT>ram :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>ram :itim_init + + + . = ALIGN(8); + PROVIDE( mee_segment_itim_target_end = . ); + + .lalign : { . = ALIGN(4); diff --git a/bsp/coreip-s51-arty/mee.lds b/bsp/coreip-s51-arty/mee.lds index d0434f8..c081d9f 100644 --- a/bsp/coreip-s51-arty/mee.lds +++ b/bsp/coreip-s51-arty/mee.lds @@ -5,6 +5,7 @@ ENTRY(_enter) MEMORY { ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x10000 + itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000 flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 0x20000000 } @@ -12,7 +13,9 @@ PHDRS { flash PT_LOAD; ram_init PT_LOAD; + itim_init PT_LOAD; ram PT_NULL; + itim PT_NULL; } SECTIONS @@ -117,6 +120,30 @@ SECTIONS } >flash AT>flash :flash + .litimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_target_start = . ); + } >itim AT>flash :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>flash :itim_init + + + . = ALIGN(8); + PROVIDE( mee_segment_itim_target_end = . ); + + .lalign : { . = ALIGN(4); diff --git a/bsp/coreip-s51/mee.lds b/bsp/coreip-s51/mee.lds index 9f73234..3e454a7 100644 --- a/bsp/coreip-s51/mee.lds +++ b/bsp/coreip-s51/mee.lds @@ -4,6 +4,7 @@ ENTRY(_enter) MEMORY { + itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000 ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 0x4000000 } @@ -11,7 +12,9 @@ PHDRS { flash PT_LOAD; ram_init PT_LOAD; + itim_init PT_LOAD; ram PT_LOAD; + itim PT_LOAD; } SECTIONS @@ -116,6 +119,30 @@ SECTIONS } >ram AT>ram :ram + .litimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_source_start = . ); + } >ram AT>ram :ram + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_target_start = . ); + } >itim AT>ram :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>ram :itim_init + + + . = ALIGN(8); + PROVIDE( mee_segment_itim_target_end = . ); + + .lalign : { . = ALIGN(4); diff --git a/bsp/freedom-e310-arty/mee.lds b/bsp/freedom-e310-arty/mee.lds index cf24a7c..8cd1a87 100644 --- a/bsp/freedom-e310-arty/mee.lds +++ b/bsp/freedom-e310-arty/mee.lds @@ -5,6 +5,7 @@ ENTRY(_enter) MEMORY { ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x4000 + itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000 flash (rxai!w) : ORIGIN = 0x20400000, LENGTH = 0x20000000 } @@ -12,7 +13,9 @@ PHDRS { flash PT_LOAD; ram_init PT_LOAD; + itim_init PT_LOAD; ram PT_NULL; + itim PT_NULL; } SECTIONS @@ -117,6 +120,30 @@ SECTIONS } >flash AT>flash :flash + .litimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_target_start = . ); + } >itim AT>flash :itim_init + + + .itim : + { + *(.itim .itim.*) + } >itim AT>flash :itim_init + + + . = ALIGN(8); + PROVIDE( mee_segment_itim_target_end = . ); + + .lalign : { . = ALIGN(4); diff --git a/bsp/sifive-hifive1/mee.lds b/bsp/sifive-hifive1/mee.lds index cf24a7c..5a5a1aa 100644 --- a/bsp/sifive-hifive1/mee.lds +++ b/bsp/sifive-hifive1/mee.lds @@ -12,7 +12,9 @@ PHDRS { flash PT_LOAD; ram_init PT_LOAD; + itim_init PT_LOAD; ram PT_NULL; + itim PT_NULL; } SECTIONS @@ -117,6 +119,30 @@ SECTIONS } >flash AT>flash :flash + .litimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_itim_target_start = . ); + } >ram AT>flash :ram_init + + + .itim : + { + *(.itim .itim.*) + } >flash AT>flash :flash + + + . = ALIGN(8); + PROVIDE( mee_segment_itim_target_end = . ); + + .lalign : { . = ALIGN(4); -- cgit v1.2.3 From 2139efac01f4bd8826eeec3cf5a60ffaf4d5c942 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Wed, 19 Dec 2018 14:21:37 -0800 Subject: Add ITIM example Signed-off-by: Nathaniel Graff --- .gitmodules | 3 +++ software/example-itim | 1 + 2 files changed, 4 insertions(+) create mode 160000 software/example-itim diff --git a/.gitmodules b/.gitmodules index 060615c..955d83d 100644 --- a/.gitmodules +++ b/.gitmodules @@ -7,3 +7,6 @@ [submodule "scripts/elf2hex"] path = scripts/elf2hex url = ../elf2hex +[submodule "software/example-itim"] + path = software/example-itim + url = https://github.com/sifive/example-itim.git diff --git a/software/example-itim b/software/example-itim new file mode 160000 index 0000000..bd80215 --- /dev/null +++ b/software/example-itim @@ -0,0 +1 @@ +Subproject commit bd8021596e0e157da0ffc5426bcc020044345782 -- cgit v1.2.3