From 7ad24f2558984dcf03cf58b6fc90431067e78901 Mon Sep 17 00:00:00 2001 From: cgsfv Date: Thu, 13 Jun 2019 20:36:29 +0200 Subject: Adding ref to matching QEMU repo --- bsp/qemu-sifive-e31/README.md | 2 ++ bsp/qemu-sifive-s51/README.md | 2 ++ 2 files changed, 4 insertions(+) diff --git a/bsp/qemu-sifive-e31/README.md b/bsp/qemu-sifive-e31/README.md index 9474b9f..72889b9 100644 --- a/bsp/qemu-sifive-e31/README.md +++ b/bsp/qemu-sifive-e31/README.md @@ -10,3 +10,5 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an - SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 1 RGB LEDS + +This BSP matches the QEMU code in https://github.com/sifive/riscv-qemu/tree/riscv-qemu-3.1 diff --git a/bsp/qemu-sifive-s51/README.md b/bsp/qemu-sifive-s51/README.md index 64593f3..7825a98 100644 --- a/bsp/qemu-sifive-s51/README.md +++ b/bsp/qemu-sifive-s51/README.md @@ -10,3 +10,5 @@ This target is ideal for getting familiarize with RISC-V ISA instructions set an - SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 1 RGB LEDS + +This BSP matches the QEMU code in https://github.com/sifive/riscv-qemu/tree/riscv-qemu-3.1 -- cgit v1.2.1-18-gbd029