From 64115be98dda5eae8840e373c85b0c615f196dbb Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Tue, 25 Jul 2017 16:58:47 -0500 Subject: added vectored interrupt example --- .../E51FPGA/vectored_interrupts/.cproject | 220 ++++++++++++++ .../E51FPGA/vectored_interrupts/.gitignore | 1 + FreedomStudio/E51FPGA/vectored_interrupts/.project | 233 +++++++++++++++ .../sifive-coreplexip-e51-arty.cfg | 31 ++ bsp/env/coreplexip-e31-arty/init.c | 13 +- bsp/env/coreplexip-e31-arty/platform.h | 5 + bsp/env/ventry.S | 319 +++++++++++++++++++++ software/vectored_interrupts/Makefile | 10 + software/vectored_interrupts/vectored_interrupts | Bin 0 -> 188880 bytes software/vectored_interrupts/vectored_interrupts.c | 216 ++++++++++++++ 10 files changed, 1046 insertions(+), 2 deletions(-) create mode 100644 FreedomStudio/E51FPGA/vectored_interrupts/.cproject create mode 100644 FreedomStudio/E51FPGA/vectored_interrupts/.gitignore create mode 100644 FreedomStudio/E51FPGA/vectored_interrupts/.project create mode 100644 FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg create mode 100644 bsp/env/ventry.S create mode 100644 software/vectored_interrupts/Makefile create mode 100755 software/vectored_interrupts/vectored_interrupts create mode 100644 software/vectored_interrupts/vectored_interrupts.c diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.cproject b/FreedomStudio/E51FPGA/vectored_interrupts/.cproject new file mode 100644 index 0000000..c50fa56 --- /dev/null +++ b/FreedomStudio/E51FPGA/vectored_interrupts/.cproject @@ -0,0 +1,220 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.gitignore b/FreedomStudio/E51FPGA/vectored_interrupts/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/FreedomStudio/E51FPGA/vectored_interrupts/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.project b/FreedomStudio/E51FPGA/vectored_interrupts/.project new file mode 100644 index 0000000..22e0667 --- /dev/null +++ b/FreedomStudio/E51FPGA/vectored_interrupts/.project @@ -0,0 +1,233 @@ + + + vectored_interrupts + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + bsp + 2 + virtual:/virtual + + + vectored_interrupts.c + 1 + PARENT-3-PROJECT_LOC/software/vectored_interrupts/vectored_interrupts.c + + + bsp/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/.DS_Store + + + bsp/drivers + 2 + virtual:/virtual + + + bsp/env + 2 + virtual:/virtual + + + bsp/include + 2 + virtual:/virtual + + + bsp/drivers/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/.DS_Store + + + bsp/drivers/fe300prci + 2 + virtual:/virtual + + + bsp/drivers/plic + 2 + virtual:/virtual + + + bsp/env/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/env/.DS_Store + + + bsp/env/coreplexip-arty.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h + + + bsp/env/coreplexip-e51-arty + 2 + virtual:/virtual + + + bsp/env/encoding.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/encoding.h + + + bsp/env/hifive1.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/hifive1.h + + + bsp/env/start.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/start.S + + + bsp/env/ventry.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/ventry.S + + + bsp/include/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/include/.DS_Store + + + bsp/include/sifive + 2 + virtual:/virtual + + + bsp/drivers/fe300prci/fe300prci_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c + + + bsp/drivers/fe300prci/fe300prci_driver.h + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.h + + + bsp/drivers/plic/plic_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.c + + + bsp/drivers/plic/plic_driver.h + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.h + + + bsp/env/coreplexip-e51-arty/flash.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/flash.lds + + + bsp/env/coreplexip-e51-arty/init.c + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/init.c + + + bsp/env/coreplexip-e51-arty/openocd.cfg + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/openocd.cfg + + + bsp/env/coreplexip-e51-arty/platform.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/platform.h + + + bsp/env/coreplexip-e51-arty/scratchpad.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/scratchpad.lds + + + bsp/include/sifive/bits.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h + + + bsp/include/sifive/const.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h + + + bsp/include/sifive/devices + 2 + virtual:/virtual + + + bsp/include/sifive/sections.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h + + + bsp/include/sifive/smp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h + + + bsp/include/sifive/devices/aon.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h + + + bsp/include/sifive/devices/clint.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h + + + bsp/include/sifive/devices/gpio.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h + + + bsp/include/sifive/devices/otp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h + + + bsp/include/sifive/devices/plic.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h + + + bsp/include/sifive/devices/prci.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h + + + bsp/include/sifive/devices/pwm.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h + + + bsp/include/sifive/devices/spi.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h + + + bsp/include/sifive/devices/uart.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h + + + diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg new file mode 100644 index 0000000..8b382dc --- /dev/null +++ b/FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/bsp/env/coreplexip-e31-arty/init.c b/bsp/env/coreplexip-e31-arty/init.c index 84ae09e..888f04f 100644 --- a/bsp/env/coreplexip-e31-arty/init.c +++ b/bsp/env/coreplexip-e31-arty/init.c @@ -10,8 +10,14 @@ #define XSTR(x) #x #define STR(x) XSTR(x) +#ifndef VECT_IRQ + #define TRAP_ENTRY trap_entry +#else + #define TRAP_ENTRY vtrap_entry +#endif + extern int main(int argc, char** argv); -extern void trap_entry(); +extern void TRAP_ENTRY(); static unsigned long get_cpu_freq() { @@ -57,6 +63,7 @@ typedef void (*my_interrupt_function_ptr_t) (void); extern my_interrupt_function_ptr_t localISR[]; #endif +#ifndef VECT_IRQ uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) { if (0){ @@ -81,6 +88,7 @@ uintptr_t handle_trap(uintptr_t mcause, uintptr_t epc) } return epc; } +#endif void _init() { @@ -89,7 +97,8 @@ void _init() puts("core freq at " STR(CPU_FREQ) " Hz\n"); - write_csr(mtvec, &trap_entry); + write_csr(mtvec, ((unsigned long)&TRAP_ENTRY | MTVEC_VECTORED)); + #endif } diff --git a/bsp/env/coreplexip-e31-arty/platform.h b/bsp/env/coreplexip-e31-arty/platform.h index 42c8887..307a0c6 100644 --- a/bsp/env/coreplexip-e31-arty/platform.h +++ b/bsp/env/coreplexip-e31-arty/platform.h @@ -13,6 +13,11 @@ #define MCAUSE_CAUSE 0x7FFFFFFFFFFFFFFFUL #endif +#ifdef VECT_IRQ + #define MTVEC_VECTORED 0x01 +#else + #define MTVEC_VECTORED 0x00 +#endif #define IRQ_M_LOCAL 16 #define MIP_MLIP(x) (1 << (IRQ_M_LOCAL + x)) diff --git a/bsp/env/ventry.S b/bsp/env/ventry.S new file mode 100644 index 0000000..9c2f118 --- /dev/null +++ b/bsp/env/ventry.S @@ -0,0 +1,319 @@ +// See LICENSE for license details + +#ifndef VENTRY_S +#define VENTRY_S + +#include "encoding.h" +#include "sifive/bits.h" + +.macro TRAP_ENTRY + addi sp, sp, -32*REGBYTES + + STORE x1, 1*REGBYTES(sp) + STORE x2, 2*REGBYTES(sp) + STORE x3, 3*REGBYTES(sp) + STORE x4, 4*REGBYTES(sp) + STORE x5, 5*REGBYTES(sp) + STORE x6, 6*REGBYTES(sp) + STORE x7, 7*REGBYTES(sp) + STORE x8, 8*REGBYTES(sp) + STORE x9, 9*REGBYTES(sp) + STORE x10, 10*REGBYTES(sp) + STORE x11, 11*REGBYTES(sp) + STORE x12, 12*REGBYTES(sp) + STORE x13, 13*REGBYTES(sp) + STORE x14, 14*REGBYTES(sp) + STORE x15, 15*REGBYTES(sp) + STORE x16, 16*REGBYTES(sp) + STORE x17, 17*REGBYTES(sp) + STORE x18, 18*REGBYTES(sp) + STORE x19, 19*REGBYTES(sp) + STORE x20, 20*REGBYTES(sp) + STORE x21, 21*REGBYTES(sp) + STORE x22, 22*REGBYTES(sp) + STORE x23, 23*REGBYTES(sp) + STORE x24, 24*REGBYTES(sp) + STORE x25, 25*REGBYTES(sp) + STORE x26, 26*REGBYTES(sp) + STORE x27, 27*REGBYTES(sp) + STORE x28, 28*REGBYTES(sp) + STORE x29, 29*REGBYTES(sp) + STORE x30, 30*REGBYTES(sp) + STORE x31, 31*REGBYTES(sp) +.endm + +# Remain in M-mode after mret + li t0, MSTATUS_MPP + csrs mstatus, t0 + +.macro TRAP_EXIT + LOAD x1, 1*REGBYTES(sp) + LOAD x2, 2*REGBYTES(sp) + LOAD x3, 3*REGBYTES(sp) + LOAD x4, 4*REGBYTES(sp) + LOAD x5, 5*REGBYTES(sp) + LOAD x6, 6*REGBYTES(sp) + LOAD x7, 7*REGBYTES(sp) + LOAD x8, 8*REGBYTES(sp) + LOAD x9, 9*REGBYTES(sp) + LOAD x10, 10*REGBYTES(sp) + LOAD x11, 11*REGBYTES(sp) + LOAD x12, 12*REGBYTES(sp) + LOAD x13, 13*REGBYTES(sp) + LOAD x14, 14*REGBYTES(sp) + LOAD x15, 15*REGBYTES(sp) + LOAD x16, 16*REGBYTES(sp) + LOAD x17, 17*REGBYTES(sp) + LOAD x18, 18*REGBYTES(sp) + LOAD x19, 19*REGBYTES(sp) + LOAD x20, 20*REGBYTES(sp) + LOAD x21, 21*REGBYTES(sp) + LOAD x22, 22*REGBYTES(sp) + LOAD x23, 23*REGBYTES(sp) + LOAD x24, 24*REGBYTES(sp) + LOAD x25, 25*REGBYTES(sp) + LOAD x26, 26*REGBYTES(sp) + LOAD x27, 27*REGBYTES(sp) + LOAD x28, 28*REGBYTES(sp) + LOAD x29, 29*REGBYTES(sp) + LOAD x30, 30*REGBYTES(sp) + LOAD x31, 31*REGBYTES(sp) + + addi sp, sp, 32*REGBYTES + mret +.endm + +#Vector table for E31/E51 + + .section .text.entry + .align 8 + .global vtrap_entry +vtrap_entry: + j sync_trap + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j vmsi_Handler + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j vmti_Handler + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j vmei_Handler + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j reserved + .align 2 + j vlip_Handler0 + .align 2 + j vlip_Handler1 + .align 2 + j vlip_Handler2 + .align 2 + j vlip_Handler3 + .align 2 + j vlip_Handler4 + .align 2 + .align 2 + j vlip_Handler5 + .align 2 + j vlip_Handler6 + .align 2 + j vlip_Handler7 + .align 2 + j vlip_Handler8 + .align 2 + j vlip_Handler9 + .align 2 + j vlip_Handler10 + .align 2 + j vlip_Handler11 + .align 2 + j vlip_Handler12 + .align 2 + j vlip_Handler13 + .align 2 + j vlip_Handler14 + .align 2 + j vlip_Handler15 + +#synchronous trap +sync_trap: + TRAP_ENTRY + csrr a0, mcause + csrr a1, mepc + mv a2, sp + jal handle_sync_trap + csrw mepc, a0 + TRAP_EXIT + +#Machine Software Interrupt +vmsi_Handler: + TRAP_ENTRY + jal reserved + TRAP_EXIT + +#Machine Timer Interrupt +vmti_Handler: + TRAP_ENTRY + jal handle_m_time_interrupt + TRAP_EXIT + +#Machine External Interrupt +vmei_Handler: + TRAP_ENTRY + jal handle_m_external_interrupt + TRAP_EXIT + +#LIP0 +vlip_Handler0: + TRAP_ENTRY + jal handle_local_interrupt0 + TRAP_EXIT + +#LIP1 +vlip_Handler1: + TRAP_ENTRY + jal handle_local_interrupt1 + TRAP_EXIT + +#LIP2 +vlip_Handler2: + TRAP_ENTRY + jal handle_local_interrupt2 + TRAP_EXIT + +#LIP3 +vlip_Handler3: + TRAP_ENTRY + jal handle_local_interrupt3 + TRAP_EXIT + +#LIP4 +vlip_Handler4: + TRAP_ENTRY + jal handle_local_interrupt4 + TRAP_EXIT + +#LIP5 +vlip_Handler5: + TRAP_ENTRY + jal handle_local_interrupt5 + TRAP_EXIT + +#LIP6 +vlip_Handler6: + TRAP_ENTRY + jal handle_local_interrupt6 + TRAP_EXIT + +#LIP7 +vlip_Handler7: + TRAP_ENTRY + jal handle_local_interrupt7 + TRAP_EXIT + +#LIP8 +vlip_Handler8: + TRAP_ENTRY + jal handle_local_interrupt8 + TRAP_EXIT + +#LIP9 +vlip_Handler9: + TRAP_ENTRY + jal handle_local_interrupt9 + TRAP_EXIT + +#LIP10 +vlip_Handler10: + TRAP_ENTRY + jal handle_local_interrupt10 + TRAP_EXIT + +#LIP11 +vlip_Handler11: + TRAP_ENTRY + jal handle_local_interrupt11 + TRAP_EXIT + +#LIP12 +vlip_Handler12: + TRAP_ENTRY + jal handle_local_interrupt12 + TRAP_EXIT + +#LIP13 +vlip_Handler13: + TRAP_ENTRY + jal handle_local_interrupt13 + TRAP_EXIT + +#LIP14 +vlip_Handler14: + TRAP_ENTRY + jal handle_local_interrupt14 + TRAP_EXIT + +#LIP15 +vlip_Handler15: + TRAP_ENTRY + jal handle_local_interrupt15 + TRAP_EXIT + +#unimplemented ISRs trap here +.weak reserved +reserved: +.weak handle_local_interrupt0 +handle_local_interrupt0: +.weak handle_local_interrupt1 +handle_local_interrupt1: +.weak handle_local_interrupt2 +handle_local_interrupt2: +.weak handle_local_interrupt3 +handle_local_interrupt3: +.weak handle_local_interrupt4 +handle_local_interrupt4: +.weak handle_local_interrupt5 +handle_local_interrupt5: +.weak handle_local_interrupt6 +handle_local_interrupt6: +.weak handle_local_interrupt7 +handle_local_interrupt7: +.weak handle_local_interrupt8 +handle_local_interrupt8: +.weak handle_local_interrupt9 +handle_local_interrupt9: +.weak handle_local_interrupt10 +handle_local_interrupt10: +.weak handle_local_interrupt11 +handle_local_interrupt11: +.weak handle_local_interrupt12 +handle_local_interrupt12: +.weak handle_local_interrupt13 +handle_local_interrupt13: +.weak handle_local_interrupt14 +handle_local_interrupt14: +.weak handle_local_interrupt15 +handle_local_interrupt15: +1: + j 1b + +#endif diff --git a/software/vectored_interrupts/Makefile b/software/vectored_interrupts/Makefile new file mode 100644 index 0000000..4365038 --- /dev/null +++ b/software/vectored_interrupts/Makefile @@ -0,0 +1,10 @@ +TARGET = vectored_interrupts +CFLAGS += -O2 -fno-builtin-printf -DVECT_IRQ + +BSP_BASE = ../../bsp + +ASM_SRCS += $(ENV_DIR)/ventry.S +C_SRCS += vectored_interrupts.c +C_SRCS += $(BSP_BASE)/drivers/plic/plic_driver.c + +include $(BSP_BASE)/env/common.mk diff --git a/software/vectored_interrupts/vectored_interrupts b/software/vectored_interrupts/vectored_interrupts new file mode 100755 index 0000000..fd85e7e Binary files /dev/null and b/software/vectored_interrupts/vectored_interrupts differ diff --git a/software/vectored_interrupts/vectored_interrupts.c b/software/vectored_interrupts/vectored_interrupts.c new file mode 100644 index 0000000..61eee5e --- /dev/null +++ b/software/vectored_interrupts/vectored_interrupts.c @@ -0,0 +1,216 @@ +// See LICENSE for license details. + +#include +#include +#include "platform.h" +#include +#include "plic/plic_driver.h" +#include "encoding.h" +#include + +#ifndef _SIFIVE_COREPLEXIP_ARTY_H +#error 'global_interrupts' demo only supported for Coreplex IP Eval Kits +#endif + +// Global Instance data for the PLIC +// for use by the PLIC Driver. +plic_instance_t g_plic; + +// Structures for registering different interrupt handlers +// for different parts of the application. +typedef void (*interrupt_function_ptr_t) (void); +//array of function pointers which contains the PLIC +//interrupt handlers +interrupt_function_ptr_t g_ext_interrupt_handlers[PLIC_NUM_INTERRUPTS]; + +const char * instructions_msg = " \ +\n\ + SIFIVE, INC.\n\ +E31/E51 Coreplex IP Eval Kit 'vectored_interrupts' demo. \n\ +\n\ +This demo demonstrates Vectored Interrupts capabilities of\n\ +the E31/E51 Coreplex. The vector table is defined in \n\ +bsp/env/ventry.S \n\ +Button 0 is a global external interrupt routed to the PLIC.\n\ +Button 1 is a local interrupt.\n\ +\n"; + +void print_instructions() { + + write (STDOUT_FILENO, instructions_msg, strlen(instructions_msg)); + +} + +void set_timer() { + + volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); + uint64_t now = *mtime; + uint64_t then = now + 1*RTC_FREQ; + *mtimecmp = then; + + set_csr(mie, MIP_MTIP); +} + +/*Entry Point for Machine Timer Interrupt Handler*/ +/*called from bsp/env/ventry.s */ +void handle_m_time_interrupt(){ + static uint32_t onoff=1; + + clear_csr(mie, MIP_MTIP); + + // Set Green LED + if(onoff) { + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << GREEN_LED_OFFSET) ; + onoff=0; + }else { + GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1 << GREEN_LED_OFFSET)) ; + onoff=1; + } + set_timer(); + + //re-enable button1 irq + set_csr(mie, MIP_MLIP(LOCAL_INT_BTN_1)); + +} + +/*Synchronous Trap Handler*/ +/*called from bsp/env/ventry.s */ +void handle_sync_trap(uintptr_t mcause, uintptr_t epc ) { + write(1, "vUnhandled Trap:\n", 16); + _exit(1 + mcause); +} + +/*Entry Point for PLIC Interrupt Handler*/ +/*called from bsp/env/ventry.s */ +void handle_m_external_interrupt(){ + printf("In PLIC handler\n"); + plic_source int_num = PLIC_claim_interrupt(&g_plic); + if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS)) { + g_ext_interrupt_handlers[int_num](); + } + else { + exit(1 + (uintptr_t) int_num); + } + PLIC_complete_interrupt(&g_plic, int_num); +} + +//default empty PLIC handler +void invalid_global_isr() { + printf("Unexpected global interrupt!\n"); +} + +/* b1 global interrupt isr */ +/*called from handle_m_external_interrupt */ +void button_0_handler() { + static uint32_t onoff=1; + // Set Green LED + + printf("In Button 0 handler\n"); + + if(onoff) { + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << BLUE_LED_OFFSET) ; + onoff=0; + }else { + GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1 << BLUE_LED_OFFSET)) ; + onoff=1; + } + + //clear irq - interrupt pending register is write 1 to clear + GPIO_REG(GPIO_FALL_IP) |= (1< Date: Tue, 25 Jul 2017 17:02:25 -0500 Subject: FS debug launch file --- .../vectored_interrupts OpenOCD.launch | 59 ++++++++++++++++++++++ 1 file changed, 59 insertions(+) create mode 100644 FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch b/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch new file mode 100644 index 0000000..b25a5d2 --- /dev/null +++ b/FreedomStudio/E51FPGA/vectored_interrupts/vectored_interrupts OpenOCD.launch @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.2.3 From ad2936248189d3037173ba4bc9a8b9863bb83b76 Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Tue, 25 Jul 2017 17:31:14 -0500 Subject: too many .aling 2's --- bsp/env/ventry.S | 1 - 1 file changed, 1 deletion(-) diff --git a/bsp/env/ventry.S b/bsp/env/ventry.S index 9c2f118..de6b197 100644 --- a/bsp/env/ventry.S +++ b/bsp/env/ventry.S @@ -131,7 +131,6 @@ vtrap_entry: .align 2 j vlip_Handler4 .align 2 - .align 2 j vlip_Handler5 .align 2 j vlip_Handler6 -- cgit v1.2.3 From db71fcb94796e465096bb0fa2ff579ac7477948a Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Wed, 26 Jul 2017 09:02:40 -0500 Subject: E31 FS Project --- .../E31FPGA/vectored_interrupts/.cproject | 219 ++++++++++++++++++++ .../E31FPGA/vectored_interrupts/.gitignore | 1 + FreedomStudio/E31FPGA/vectored_interrupts/.project | 228 +++++++++++++++++++++ .../sifive-coreplexip-e31-arty.cfg | 31 +++ .../vectored_interrupts Debug.launch | 59 ++++++ 5 files changed, 538 insertions(+) create mode 100644 FreedomStudio/E31FPGA/vectored_interrupts/.cproject create mode 100644 FreedomStudio/E31FPGA/vectored_interrupts/.gitignore create mode 100644 FreedomStudio/E31FPGA/vectored_interrupts/.project create mode 100644 FreedomStudio/E31FPGA/vectored_interrupts/sifive-coreplexip-e31-arty.cfg create mode 100644 FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts Debug.launch diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/.cproject b/FreedomStudio/E31FPGA/vectored_interrupts/.cproject new file mode 100644 index 0000000..8d8ac7e --- /dev/null +++ b/FreedomStudio/E31FPGA/vectored_interrupts/.cproject @@ -0,0 +1,219 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/.gitignore b/FreedomStudio/E31FPGA/vectored_interrupts/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/FreedomStudio/E31FPGA/vectored_interrupts/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/.project b/FreedomStudio/E31FPGA/vectored_interrupts/.project new file mode 100644 index 0000000..331760e --- /dev/null +++ b/FreedomStudio/E31FPGA/vectored_interrupts/.project @@ -0,0 +1,228 @@ + + + vectored_interrupts + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + bsp + 2 + virtual:/virtual + + + bsp/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/.DS_Store + + + bsp/drivers + 2 + virtual:/virtual + + + bsp/env + 2 + virtual:/virtual + + + bsp/include + 2 + virtual:/virtual + + + bsp/drivers/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/.DS_Store + + + bsp/drivers/fe300prci + 2 + virtual:/virtual + + + bsp/drivers/plic + 2 + virtual:/virtual + + + bsp/env/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/env/.DS_Store + + + bsp/env/coreplexip-arty.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h + + + bsp/env/coreplexip-e31-arty + 2 + virtual:/virtual + + + bsp/env/encoding.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/encoding.h + + + bsp/env/start.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/start.S + + + bsp/env/ventry.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/ventry.S + + + bsp/include/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/include/.DS_Store + + + bsp/include/sifive + 2 + virtual:/virtual + + + bsp/drivers/fe300prci/fe300prci_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c + + + bsp/drivers/fe300prci/fe300prci_driver.h + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.h + + + bsp/drivers/plic/plic_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.c + + + bsp/drivers/plic/plic_driver.h + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.h + + + bsp/env/coreplexip-e31-arty/flash.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/flash.lds + + + bsp/env/coreplexip-e31-arty/init.c + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/init.c + + + bsp/env/coreplexip-e31-arty/openocd.cfg + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/openocd.cfg + + + bsp/env/coreplexip-e31-arty/platform.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/platform.h + + + bsp/env/coreplexip-e31-arty/scratchpad.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/scratchpad.lds + + + bsp/env/coreplexip-e31-arty/settings.mk + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/settings.mk + + + bsp/include/sifive/bits.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h + + + bsp/include/sifive/const.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h + + + bsp/include/sifive/devices + 2 + virtual:/virtual + + + bsp/include/sifive/sections.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h + + + bsp/include/sifive/smp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h + + + bsp/include/sifive/devices/aon.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h + + + bsp/include/sifive/devices/clint.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h + + + bsp/include/sifive/devices/gpio.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h + + + bsp/include/sifive/devices/otp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h + + + bsp/include/sifive/devices/plic.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h + + + bsp/include/sifive/devices/prci.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h + + + bsp/include/sifive/devices/pwm.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h + + + bsp/include/sifive/devices/spi.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h + + + bsp/include/sifive/devices/uart.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h + + + diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/sifive-coreplexip-e31-arty.cfg b/FreedomStudio/E31FPGA/vectored_interrupts/sifive-coreplexip-e31-arty.cfg new file mode 100644 index 0000000..8b382dc --- /dev/null +++ b/FreedomStudio/E31FPGA/vectored_interrupts/sifive-coreplexip-e31-arty.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts Debug.launch b/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts Debug.launch new file mode 100644 index 0000000..73f5aaa --- /dev/null +++ b/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts Debug.launch @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + -- cgit v1.2.3 From 595d44b8c7857ff2aacc588ffcc54a1d1b763a65 Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Wed, 26 Jul 2017 09:04:08 -0500 Subject: fixed TRAP_EXIT macro. TRAP_ENTRY/EXIT2 only saves/restores callee registers --- bsp/env/ventry.S | 59 +++++++++++++++++++++++++++++++++++++++++++++++++------- 1 file changed, 52 insertions(+), 7 deletions(-) diff --git a/bsp/env/ventry.S b/bsp/env/ventry.S index de6b197..ed79789 100644 --- a/bsp/env/ventry.S +++ b/bsp/env/ventry.S @@ -42,11 +42,11 @@ STORE x31, 31*REGBYTES(sp) .endm +.macro TRAP_EXIT # Remain in M-mode after mret li t0, MSTATUS_MPP csrs mstatus, t0 -.macro TRAP_EXIT LOAD x1, 1*REGBYTES(sp) LOAD x2, 2*REGBYTES(sp) LOAD x3, 3*REGBYTES(sp) @@ -83,6 +83,51 @@ mret .endm + + +.macro TRAP_ENTRY2 + addi sp, sp, -14*REGBYTES + + STORE x2, 1*REGBYTES(sp) + STORE x8, 2*REGBYTES(sp) + STORE x9, 3*REGBYTES(sp) + STORE x18, 4*REGBYTES(sp) + STORE x19, 5*REGBYTES(sp) + STORE x20, 6*REGBYTES(sp) + STORE x21, 7*REGBYTES(sp) + STORE x22, 8*REGBYTES(sp) + STORE x23, 9*REGBYTES(sp) + STORE x24, 10*REGBYTES(sp) + STORE x25, 11*REGBYTES(sp) + STORE x26, 12*REGBYTES(sp) + STORE x27, 13*REGBYTES(sp) +.endm + +.macro TRAP_EXIT2 +# Remain in M-mode after mret + li t0, MSTATUS_MPP + csrs mstatus, t0 + + LOAD x3, 1*REGBYTES(sp) + LOAD x8, 2*REGBYTES(sp) + LOAD x9, 3*REGBYTES(sp) + LOAD x18, 4*REGBYTES(sp) + LOAD x19, 5*REGBYTES(sp) + LOAD x20, 6*REGBYTES(sp) + LOAD x21, 7*REGBYTES(sp) + LOAD x22, 8*REGBYTES(sp) + LOAD x23, 9*REGBYTES(sp) + LOAD x24, 10*REGBYTES(sp) + LOAD x25, 11*REGBYTES(sp) + LOAD x26, 12*REGBYTES(sp) + LOAD x27, 13*REGBYTES(sp) + + addi sp, sp, 14*REGBYTES + mret +.endm + + + #Vector table for E31/E51 .section .text.entry @@ -171,15 +216,15 @@ vmsi_Handler: #Machine Timer Interrupt vmti_Handler: - TRAP_ENTRY + TRAP_ENTRY2 jal handle_m_time_interrupt - TRAP_EXIT + TRAP_EXIT2 #Machine External Interrupt vmei_Handler: - TRAP_ENTRY + TRAP_ENTRY2 jal handle_m_external_interrupt - TRAP_EXIT + TRAP_EXIT2 #LIP0 vlip_Handler0: @@ -213,9 +258,9 @@ vlip_Handler4: #LIP5 vlip_Handler5: - TRAP_ENTRY + TRAP_ENTRY2 jal handle_local_interrupt5 - TRAP_EXIT + TRAP_EXIT2 #LIP6 vlip_Handler6: -- cgit v1.2.3 From 14d6a986479e3c0e8b78e05d751cddce2ef83897 Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Wed, 26 Jul 2017 09:05:05 -0500 Subject: fixed comments --- software/vectored_interrupts/vectored_interrupts.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/software/vectored_interrupts/vectored_interrupts.c b/software/vectored_interrupts/vectored_interrupts.c index 61eee5e..8958105 100644 --- a/software/vectored_interrupts/vectored_interrupts.c +++ b/software/vectored_interrupts/vectored_interrupts.c @@ -100,7 +100,7 @@ void invalid_global_isr() { printf("Unexpected global interrupt!\n"); } -/* b1 global interrupt isr */ +/* b0 global interrupt isr */ /*called from handle_m_external_interrupt */ void button_0_handler() { static uint32_t onoff=1; @@ -136,7 +136,7 @@ void handle_local_interrupt5() { onoff=1; } - //debounce by turing off until next timer tick + //debounce by turning off until next timer tick clear_csr(mie, MIP_MLIP(LOCAL_INT_BTN_1)); } -- cgit v1.2.3 From 1f845553419f4683312cd0f8f7a3ecc9e5f09609 Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Wed, 26 Jul 2017 09:07:19 -0500 Subject: removed bin file commited by accident --- software/vectored_interrupts/vectored_interrupts | Bin 188880 -> 0 bytes 1 file changed, 0 insertions(+), 0 deletions(-) delete mode 100755 software/vectored_interrupts/vectored_interrupts diff --git a/software/vectored_interrupts/vectored_interrupts b/software/vectored_interrupts/vectored_interrupts deleted file mode 100755 index fd85e7e..0000000 Binary files a/software/vectored_interrupts/vectored_interrupts and /dev/null differ -- cgit v1.2.3 From e008ed03839d46388f184206d634021fd083dc78 Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Wed, 26 Jul 2017 14:55:16 -0500 Subject: only save/restore "caller" registers on trap entry --- .../vectored_interrupts/vectored_interrupts.c | 216 +++++++++++++++++++++ 1 file changed, 216 insertions(+) create mode 100644 FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts.c diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts.c b/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts.c new file mode 100644 index 0000000..8958105 --- /dev/null +++ b/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts.c @@ -0,0 +1,216 @@ +// See LICENSE for license details. + +#include +#include +#include "platform.h" +#include +#include "plic/plic_driver.h" +#include "encoding.h" +#include + +#ifndef _SIFIVE_COREPLEXIP_ARTY_H +#error 'global_interrupts' demo only supported for Coreplex IP Eval Kits +#endif + +// Global Instance data for the PLIC +// for use by the PLIC Driver. +plic_instance_t g_plic; + +// Structures for registering different interrupt handlers +// for different parts of the application. +typedef void (*interrupt_function_ptr_t) (void); +//array of function pointers which contains the PLIC +//interrupt handlers +interrupt_function_ptr_t g_ext_interrupt_handlers[PLIC_NUM_INTERRUPTS]; + +const char * instructions_msg = " \ +\n\ + SIFIVE, INC.\n\ +E31/E51 Coreplex IP Eval Kit 'vectored_interrupts' demo. \n\ +\n\ +This demo demonstrates Vectored Interrupts capabilities of\n\ +the E31/E51 Coreplex. The vector table is defined in \n\ +bsp/env/ventry.S \n\ +Button 0 is a global external interrupt routed to the PLIC.\n\ +Button 1 is a local interrupt.\n\ +\n"; + +void print_instructions() { + + write (STDOUT_FILENO, instructions_msg, strlen(instructions_msg)); + +} + +void set_timer() { + + volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); + uint64_t now = *mtime; + uint64_t then = now + 1*RTC_FREQ; + *mtimecmp = then; + + set_csr(mie, MIP_MTIP); +} + +/*Entry Point for Machine Timer Interrupt Handler*/ +/*called from bsp/env/ventry.s */ +void handle_m_time_interrupt(){ + static uint32_t onoff=1; + + clear_csr(mie, MIP_MTIP); + + // Set Green LED + if(onoff) { + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << GREEN_LED_OFFSET) ; + onoff=0; + }else { + GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1 << GREEN_LED_OFFSET)) ; + onoff=1; + } + set_timer(); + + //re-enable button1 irq + set_csr(mie, MIP_MLIP(LOCAL_INT_BTN_1)); + +} + +/*Synchronous Trap Handler*/ +/*called from bsp/env/ventry.s */ +void handle_sync_trap(uintptr_t mcause, uintptr_t epc ) { + write(1, "vUnhandled Trap:\n", 16); + _exit(1 + mcause); +} + +/*Entry Point for PLIC Interrupt Handler*/ +/*called from bsp/env/ventry.s */ +void handle_m_external_interrupt(){ + printf("In PLIC handler\n"); + plic_source int_num = PLIC_claim_interrupt(&g_plic); + if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS)) { + g_ext_interrupt_handlers[int_num](); + } + else { + exit(1 + (uintptr_t) int_num); + } + PLIC_complete_interrupt(&g_plic, int_num); +} + +//default empty PLIC handler +void invalid_global_isr() { + printf("Unexpected global interrupt!\n"); +} + +/* b0 global interrupt isr */ +/*called from handle_m_external_interrupt */ +void button_0_handler() { + static uint32_t onoff=1; + // Set Green LED + + printf("In Button 0 handler\n"); + + if(onoff) { + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << BLUE_LED_OFFSET) ; + onoff=0; + }else { + GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1 << BLUE_LED_OFFSET)) ; + onoff=1; + } + + //clear irq - interrupt pending register is write 1 to clear + GPIO_REG(GPIO_FALL_IP) |= (1< Date: Wed, 26 Jul 2017 14:59:11 -0500 Subject: only save/restore caller registers on trap entry --- bsp/env/ventry.S | 161 ++++++++++++++++--------------------------------------- 1 file changed, 46 insertions(+), 115 deletions(-) diff --git a/bsp/env/ventry.S b/bsp/env/ventry.S index ed79789..6b672e5 100644 --- a/bsp/env/ventry.S +++ b/bsp/env/ventry.S @@ -6,123 +6,54 @@ #include "encoding.h" #include "sifive/bits.h" +#only save caller registers .macro TRAP_ENTRY - addi sp, sp, -32*REGBYTES - - STORE x1, 1*REGBYTES(sp) - STORE x2, 2*REGBYTES(sp) - STORE x3, 3*REGBYTES(sp) - STORE x4, 4*REGBYTES(sp) - STORE x5, 5*REGBYTES(sp) - STORE x6, 6*REGBYTES(sp) - STORE x7, 7*REGBYTES(sp) - STORE x8, 8*REGBYTES(sp) - STORE x9, 9*REGBYTES(sp) - STORE x10, 10*REGBYTES(sp) - STORE x11, 11*REGBYTES(sp) - STORE x12, 12*REGBYTES(sp) - STORE x13, 13*REGBYTES(sp) - STORE x14, 14*REGBYTES(sp) - STORE x15, 15*REGBYTES(sp) - STORE x16, 16*REGBYTES(sp) - STORE x17, 17*REGBYTES(sp) - STORE x18, 18*REGBYTES(sp) - STORE x19, 19*REGBYTES(sp) - STORE x20, 20*REGBYTES(sp) - STORE x21, 21*REGBYTES(sp) - STORE x22, 22*REGBYTES(sp) - STORE x23, 23*REGBYTES(sp) - STORE x24, 24*REGBYTES(sp) - STORE x25, 25*REGBYTES(sp) - STORE x26, 26*REGBYTES(sp) - STORE x27, 27*REGBYTES(sp) - STORE x28, 28*REGBYTES(sp) - STORE x29, 29*REGBYTES(sp) - STORE x30, 30*REGBYTES(sp) - STORE x31, 31*REGBYTES(sp) + addi sp, sp, -18*REGBYTES + + STORE x1, 1*REGBYTES(sp) + STORE x5, 2*REGBYTES(sp) + STORE x6, 3*REGBYTES(sp) + STORE x7, 4*REGBYTES(sp) + STORE x10, 5*REGBYTES(sp) + STORE x11, 6*REGBYTES(sp) + STORE x12, 7*REGBYTES(sp) + STORE x13, 8*REGBYTES(sp) + STORE x14, 9*REGBYTES(sp) + STORE x15, 10*REGBYTES(sp) + STORE x16, 11*REGBYTES(sp) + STORE x17, 12*REGBYTES(sp) + STORE x18, 13*REGBYTES(sp) + STORE x28, 14*REGBYTES(sp) + STORE x29, 15*REGBYTES(sp) + STORE x30, 16*REGBYTES(sp) + STORE x31, 17*REGBYTES(sp) .endm +#restore caller registers .macro TRAP_EXIT # Remain in M-mode after mret li t0, MSTATUS_MPP csrs mstatus, t0 - LOAD x1, 1*REGBYTES(sp) - LOAD x2, 2*REGBYTES(sp) - LOAD x3, 3*REGBYTES(sp) - LOAD x4, 4*REGBYTES(sp) - LOAD x5, 5*REGBYTES(sp) - LOAD x6, 6*REGBYTES(sp) - LOAD x7, 7*REGBYTES(sp) - LOAD x8, 8*REGBYTES(sp) - LOAD x9, 9*REGBYTES(sp) - LOAD x10, 10*REGBYTES(sp) - LOAD x11, 11*REGBYTES(sp) - LOAD x12, 12*REGBYTES(sp) - LOAD x13, 13*REGBYTES(sp) - LOAD x14, 14*REGBYTES(sp) - LOAD x15, 15*REGBYTES(sp) - LOAD x16, 16*REGBYTES(sp) - LOAD x17, 17*REGBYTES(sp) - LOAD x18, 18*REGBYTES(sp) - LOAD x19, 19*REGBYTES(sp) - LOAD x20, 20*REGBYTES(sp) - LOAD x21, 21*REGBYTES(sp) - LOAD x22, 22*REGBYTES(sp) - LOAD x23, 23*REGBYTES(sp) - LOAD x24, 24*REGBYTES(sp) - LOAD x25, 25*REGBYTES(sp) - LOAD x26, 26*REGBYTES(sp) - LOAD x27, 27*REGBYTES(sp) - LOAD x28, 28*REGBYTES(sp) - LOAD x29, 29*REGBYTES(sp) - LOAD x30, 30*REGBYTES(sp) - LOAD x31, 31*REGBYTES(sp) - - addi sp, sp, 32*REGBYTES - mret -.endm - - - -.macro TRAP_ENTRY2 - addi sp, sp, -14*REGBYTES - - STORE x2, 1*REGBYTES(sp) - STORE x8, 2*REGBYTES(sp) - STORE x9, 3*REGBYTES(sp) - STORE x18, 4*REGBYTES(sp) - STORE x19, 5*REGBYTES(sp) - STORE x20, 6*REGBYTES(sp) - STORE x21, 7*REGBYTES(sp) - STORE x22, 8*REGBYTES(sp) - STORE x23, 9*REGBYTES(sp) - STORE x24, 10*REGBYTES(sp) - STORE x25, 11*REGBYTES(sp) - STORE x26, 12*REGBYTES(sp) - STORE x27, 13*REGBYTES(sp) -.endm - -.macro TRAP_EXIT2 -# Remain in M-mode after mret - li t0, MSTATUS_MPP - csrs mstatus, t0 - - LOAD x3, 1*REGBYTES(sp) - LOAD x8, 2*REGBYTES(sp) - LOAD x9, 3*REGBYTES(sp) - LOAD x18, 4*REGBYTES(sp) - LOAD x19, 5*REGBYTES(sp) - LOAD x20, 6*REGBYTES(sp) - LOAD x21, 7*REGBYTES(sp) - LOAD x22, 8*REGBYTES(sp) - LOAD x23, 9*REGBYTES(sp) - LOAD x24, 10*REGBYTES(sp) - LOAD x25, 11*REGBYTES(sp) - LOAD x26, 12*REGBYTES(sp) - LOAD x27, 13*REGBYTES(sp) - - addi sp, sp, 14*REGBYTES + LOAD x1, 1*REGBYTES(sp) + LOAD x5, 2*REGBYTES(sp) + LOAD x6, 3*REGBYTES(sp) + LOAD x7, 4*REGBYTES(sp) + LOAD x10, 5*REGBYTES(sp) + LOAD x11, 6*REGBYTES(sp) + LOAD x12, 7*REGBYTES(sp) + LOAD x13, 8*REGBYTES(sp) + LOAD x14, 9*REGBYTES(sp) + LOAD x15, 10*REGBYTES(sp) + LOAD x16, 11*REGBYTES(sp) + LOAD x17, 12*REGBYTES(sp) + LOAD x18, 13*REGBYTES(sp) + LOAD x28, 14*REGBYTES(sp) + LOAD x29, 15*REGBYTES(sp) + LOAD x30, 16*REGBYTES(sp) + LOAD x31, 17*REGBYTES(sp) + + addi sp, sp, 18*REGBYTES mret .endm @@ -216,15 +147,15 @@ vmsi_Handler: #Machine Timer Interrupt vmti_Handler: - TRAP_ENTRY2 + TRAP_ENTRY jal handle_m_time_interrupt - TRAP_EXIT2 + TRAP_EXIT #Machine External Interrupt vmei_Handler: - TRAP_ENTRY2 + TRAP_ENTRY jal handle_m_external_interrupt - TRAP_EXIT2 + TRAP_EXIT #LIP0 vlip_Handler0: @@ -258,9 +189,9 @@ vlip_Handler4: #LIP5 vlip_Handler5: - TRAP_ENTRY2 + TRAP_ENTRY jal handle_local_interrupt5 - TRAP_EXIT2 + TRAP_EXIT #LIP6 vlip_Handler6: -- cgit v1.2.3 From e05c4adbe47267b8646e683fdf9565cecf7efc95 Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Wed, 26 Jul 2017 15:04:16 -0500 Subject: E31 vectored_interrupt.c as a linked file --- FreedomStudio/E31FPGA/vectored_interrupts/.project | 5 + .../vectored_interrupts/vectored_interrupts.c | 216 --------------------- 2 files changed, 5 insertions(+), 216 deletions(-) delete mode 100644 FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts.c diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/.project b/FreedomStudio/E31FPGA/vectored_interrupts/.project index 331760e..f34dc51 100644 --- a/FreedomStudio/E31FPGA/vectored_interrupts/.project +++ b/FreedomStudio/E31FPGA/vectored_interrupts/.project @@ -29,6 +29,11 @@ 2 virtual:/virtual + + vectored_interrupts.c + 1 + PARENT-3-PROJECT_LOC/software/vectored_interrupts/vectored_interrupts.c + bsp/.DS_Store 1 diff --git a/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts.c b/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts.c deleted file mode 100644 index 8958105..0000000 --- a/FreedomStudio/E31FPGA/vectored_interrupts/vectored_interrupts.c +++ /dev/null @@ -1,216 +0,0 @@ -// See LICENSE for license details. - -#include -#include -#include "platform.h" -#include -#include "plic/plic_driver.h" -#include "encoding.h" -#include - -#ifndef _SIFIVE_COREPLEXIP_ARTY_H -#error 'global_interrupts' demo only supported for Coreplex IP Eval Kits -#endif - -// Global Instance data for the PLIC -// for use by the PLIC Driver. -plic_instance_t g_plic; - -// Structures for registering different interrupt handlers -// for different parts of the application. -typedef void (*interrupt_function_ptr_t) (void); -//array of function pointers which contains the PLIC -//interrupt handlers -interrupt_function_ptr_t g_ext_interrupt_handlers[PLIC_NUM_INTERRUPTS]; - -const char * instructions_msg = " \ -\n\ - SIFIVE, INC.\n\ -E31/E51 Coreplex IP Eval Kit 'vectored_interrupts' demo. \n\ -\n\ -This demo demonstrates Vectored Interrupts capabilities of\n\ -the E31/E51 Coreplex. The vector table is defined in \n\ -bsp/env/ventry.S \n\ -Button 0 is a global external interrupt routed to the PLIC.\n\ -Button 1 is a local interrupt.\n\ -\n"; - -void print_instructions() { - - write (STDOUT_FILENO, instructions_msg, strlen(instructions_msg)); - -} - -void set_timer() { - - volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); - volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); - uint64_t now = *mtime; - uint64_t then = now + 1*RTC_FREQ; - *mtimecmp = then; - - set_csr(mie, MIP_MTIP); -} - -/*Entry Point for Machine Timer Interrupt Handler*/ -/*called from bsp/env/ventry.s */ -void handle_m_time_interrupt(){ - static uint32_t onoff=1; - - clear_csr(mie, MIP_MTIP); - - // Set Green LED - if(onoff) { - GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << GREEN_LED_OFFSET) ; - onoff=0; - }else { - GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1 << GREEN_LED_OFFSET)) ; - onoff=1; - } - set_timer(); - - //re-enable button1 irq - set_csr(mie, MIP_MLIP(LOCAL_INT_BTN_1)); - -} - -/*Synchronous Trap Handler*/ -/*called from bsp/env/ventry.s */ -void handle_sync_trap(uintptr_t mcause, uintptr_t epc ) { - write(1, "vUnhandled Trap:\n", 16); - _exit(1 + mcause); -} - -/*Entry Point for PLIC Interrupt Handler*/ -/*called from bsp/env/ventry.s */ -void handle_m_external_interrupt(){ - printf("In PLIC handler\n"); - plic_source int_num = PLIC_claim_interrupt(&g_plic); - if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS)) { - g_ext_interrupt_handlers[int_num](); - } - else { - exit(1 + (uintptr_t) int_num); - } - PLIC_complete_interrupt(&g_plic, int_num); -} - -//default empty PLIC handler -void invalid_global_isr() { - printf("Unexpected global interrupt!\n"); -} - -/* b0 global interrupt isr */ -/*called from handle_m_external_interrupt */ -void button_0_handler() { - static uint32_t onoff=1; - // Set Green LED - - printf("In Button 0 handler\n"); - - if(onoff) { - GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << BLUE_LED_OFFSET) ; - onoff=0; - }else { - GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1 << BLUE_LED_OFFSET)) ; - onoff=1; - } - - //clear irq - interrupt pending register is write 1 to clear - GPIO_REG(GPIO_FALL_IP) |= (1< Date: Wed, 26 Jul 2017 15:18:25 -0500 Subject: removed save/restore of x18 --- bsp/env/ventry.S | 22 ++++++++++------------ 1 file changed, 10 insertions(+), 12 deletions(-) diff --git a/bsp/env/ventry.S b/bsp/env/ventry.S index 6b672e5..5cdd4b7 100644 --- a/bsp/env/ventry.S +++ b/bsp/env/ventry.S @@ -8,7 +8,7 @@ #only save caller registers .macro TRAP_ENTRY - addi sp, sp, -18*REGBYTES + addi sp, sp, -17*REGBYTES STORE x1, 1*REGBYTES(sp) STORE x5, 2*REGBYTES(sp) @@ -22,11 +22,10 @@ STORE x15, 10*REGBYTES(sp) STORE x16, 11*REGBYTES(sp) STORE x17, 12*REGBYTES(sp) - STORE x18, 13*REGBYTES(sp) - STORE x28, 14*REGBYTES(sp) - STORE x29, 15*REGBYTES(sp) - STORE x30, 16*REGBYTES(sp) - STORE x31, 17*REGBYTES(sp) + STORE x28, 13*REGBYTES(sp) + STORE x29, 14*REGBYTES(sp) + STORE x30, 15*REGBYTES(sp) + STORE x31, 16*REGBYTES(sp) .endm #restore caller registers @@ -47,13 +46,12 @@ LOAD x15, 10*REGBYTES(sp) LOAD x16, 11*REGBYTES(sp) LOAD x17, 12*REGBYTES(sp) - LOAD x18, 13*REGBYTES(sp) - LOAD x28, 14*REGBYTES(sp) - LOAD x29, 15*REGBYTES(sp) - LOAD x30, 16*REGBYTES(sp) - LOAD x31, 17*REGBYTES(sp) + LOAD x28, 13*REGBYTES(sp) + LOAD x29, 14*REGBYTES(sp) + LOAD x30, 15*REGBYTES(sp) + LOAD x31, 16*REGBYTES(sp) - addi sp, sp, 18*REGBYTES + addi sp, sp, 17*REGBYTES mret .endm -- cgit v1.2.3 From 7ce4b61da3e41c441c3634352782abc9819adf39 Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Wed, 26 Jul 2017 15:49:18 -0500 Subject: changed synch trap entry to match other vectors --- bsp/env/ventry.S | 72 ++++++++++------------ software/vectored_interrupts/vectored_interrupts.c | 4 +- 2 files changed, 36 insertions(+), 40 deletions(-) diff --git a/bsp/env/ventry.S b/bsp/env/ventry.S index 5cdd4b7..5c82c48 100644 --- a/bsp/env/ventry.S +++ b/bsp/env/ventry.S @@ -8,24 +8,24 @@ #only save caller registers .macro TRAP_ENTRY - addi sp, sp, -17*REGBYTES + addi sp, sp, -16*REGBYTES - STORE x1, 1*REGBYTES(sp) - STORE x5, 2*REGBYTES(sp) - STORE x6, 3*REGBYTES(sp) - STORE x7, 4*REGBYTES(sp) - STORE x10, 5*REGBYTES(sp) - STORE x11, 6*REGBYTES(sp) - STORE x12, 7*REGBYTES(sp) - STORE x13, 8*REGBYTES(sp) - STORE x14, 9*REGBYTES(sp) - STORE x15, 10*REGBYTES(sp) - STORE x16, 11*REGBYTES(sp) - STORE x17, 12*REGBYTES(sp) - STORE x28, 13*REGBYTES(sp) - STORE x29, 14*REGBYTES(sp) - STORE x30, 15*REGBYTES(sp) - STORE x31, 16*REGBYTES(sp) + STORE x1, 0*REGBYTES(sp) + STORE x5, 1*REGBYTES(sp) + STORE x6, 2*REGBYTES(sp) + STORE x7, 3*REGBYTES(sp) + STORE x10, 4*REGBYTES(sp) + STORE x11, 5*REGBYTES(sp) + STORE x12, 6*REGBYTES(sp) + STORE x13, 7*REGBYTES(sp) + STORE x14, 8*REGBYTES(sp) + STORE x15, 9*REGBYTES(sp) + STORE x16, 10*REGBYTES(sp) + STORE x17, 11*REGBYTES(sp) + STORE x28, 12*REGBYTES(sp) + STORE x29, 13*REGBYTES(sp) + STORE x30, 14*REGBYTES(sp) + STORE x31, 15*REGBYTES(sp) .endm #restore caller registers @@ -34,24 +34,24 @@ li t0, MSTATUS_MPP csrs mstatus, t0 - LOAD x1, 1*REGBYTES(sp) - LOAD x5, 2*REGBYTES(sp) - LOAD x6, 3*REGBYTES(sp) - LOAD x7, 4*REGBYTES(sp) - LOAD x10, 5*REGBYTES(sp) - LOAD x11, 6*REGBYTES(sp) - LOAD x12, 7*REGBYTES(sp) - LOAD x13, 8*REGBYTES(sp) - LOAD x14, 9*REGBYTES(sp) - LOAD x15, 10*REGBYTES(sp) - LOAD x16, 11*REGBYTES(sp) - LOAD x17, 12*REGBYTES(sp) - LOAD x28, 13*REGBYTES(sp) - LOAD x29, 14*REGBYTES(sp) - LOAD x30, 15*REGBYTES(sp) - LOAD x31, 16*REGBYTES(sp) + LOAD x1, 0*REGBYTES(sp) + LOAD x5, 1*REGBYTES(sp) + LOAD x6, 2*REGBYTES(sp) + LOAD x7, 3*REGBYTES(sp) + LOAD x10, 4*REGBYTES(sp) + LOAD x11, 5*REGBYTES(sp) + LOAD x12, 6*REGBYTES(sp) + LOAD x13, 7*REGBYTES(sp) + LOAD x14, 8*REGBYTES(sp) + LOAD x15, 9*REGBYTES(sp) + LOAD x16, 10*REGBYTES(sp) + LOAD x17, 11*REGBYTES(sp) + LOAD x28, 12*REGBYTES(sp) + LOAD x29, 13*REGBYTES(sp) + LOAD x30, 14*REGBYTES(sp) + LOAD x31, 15*REGBYTES(sp) - addi sp, sp, 17*REGBYTES + addi sp, sp, 16*REGBYTES mret .endm @@ -130,11 +130,7 @@ vtrap_entry: #synchronous trap sync_trap: TRAP_ENTRY - csrr a0, mcause - csrr a1, mepc - mv a2, sp jal handle_sync_trap - csrw mepc, a0 TRAP_EXIT #Machine Software Interrupt diff --git a/software/vectored_interrupts/vectored_interrupts.c b/software/vectored_interrupts/vectored_interrupts.c index 8958105..06b9620 100644 --- a/software/vectored_interrupts/vectored_interrupts.c +++ b/software/vectored_interrupts/vectored_interrupts.c @@ -76,9 +76,9 @@ void handle_m_time_interrupt(){ /*Synchronous Trap Handler*/ /*called from bsp/env/ventry.s */ -void handle_sync_trap(uintptr_t mcause, uintptr_t epc ) { +void handle_sync_trap( ) { write(1, "vUnhandled Trap:\n", 16); - _exit(1 + mcause); + _exit(1 + read_csr(mcause)); } /*Entry Point for PLIC Interrupt Handler*/ -- cgit v1.2.3