From e18401806b38ca0f60394780191df4b72cb2f88a Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Mon, 25 Feb 2019 18:57:35 -0800 Subject: Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty --- bsp/coreip-e20/README.md | 6 ++++++ bsp/coreip-e21/README.md | 6 ++++++ bsp/coreip-e31-arty/README.md | 14 ++++++++++++++ bsp/coreip-e31/README.md | 9 +++++++++ bsp/coreip-s51-arty/README.md | 13 +++++++++++++ bsp/coreip-s51/README.md | 8 ++++++++ bsp/sifive-hifive1/README.md | 12 ++++++++++++ 7 files changed, 68 insertions(+) create mode 100644 bsp/coreip-e20/README.md create mode 100644 bsp/coreip-e21/README.md create mode 100644 bsp/coreip-e31-arty/README.md create mode 100644 bsp/coreip-e31/README.md create mode 100644 bsp/coreip-s51-arty/README.md create mode 100644 bsp/coreip-s51/README.md create mode 100644 bsp/sifive-hifive1/README.md diff --git a/bsp/coreip-e20/README.md b/bsp/coreip-e20/README.md new file mode 100644 index 0000000..5e19221 --- /dev/null +++ b/bsp/coreip-e20/README.md @@ -0,0 +1,6 @@ +The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV32IMC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 4 regions diff --git a/bsp/coreip-e21/README.md b/bsp/coreip-e21/README.md new file mode 100644 index 0000000..31719b3 --- /dev/null +++ b/bsp/coreip-e21/README.md @@ -0,0 +1,6 @@ +The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV32IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 4 regions diff --git a/bsp/coreip-e31-arty/README.md b/bsp/coreip-e31-arty/README.md new file mode 100644 index 0000000..1ae8739 --- /dev/null +++ b/bsp/coreip-e31-arty/README.md @@ -0,0 +1,14 @@ +The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. + +This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV32IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 8 regions + - 16 local interrupts signal that can be connected to off core complex devices + - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels + - GPIO memory with 16 interrupt lines + - SPI memory with 1 intterupt line + - Serial port with 1 interrupt line + - 4 RGB LEDS + - 4 Buttons and 4 Switches +~ diff --git a/bsp/coreip-e31/README.md b/bsp/coreip-e31/README.md new file mode 100644 index 0000000..02f7723 --- /dev/null +++ b/bsp/coreip-e31/README.md @@ -0,0 +1,9 @@ +The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV32IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 8 regions + - 16 local interrupts signal that can be connected to off core complex devices + - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +~ diff --git a/bsp/coreip-s51-arty/README.md b/bsp/coreip-s51-arty/README.md new file mode 100644 index 0000000..6d6c04f --- /dev/null +++ b/bsp/coreip-s51-arty/README.md @@ -0,0 +1,13 @@ +The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications + +This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV64IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 8 regions + - 16 local interrupts signal that can be connected to off core complex devices + - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels + - GPIO memory with 16 interrupt lines + - SPI memory with 1 intterupt line + - Serial port with 1 interrupt line + - 4 RGB LEDS + - 4 Buttons and 4 Switches diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md new file mode 100644 index 0000000..3aa021f --- /dev/null +++ b/bsp/coreip-s51/README.md @@ -0,0 +1,8 @@ +The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV64IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 8 regions + - 16 local interrupts signal that can be connected to off core complex devices + - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md new file mode 100644 index 0000000..1cc077e --- /dev/null +++ b/bsp/sifive-hifive1/README.md @@ -0,0 +1,12 @@ +HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications. + +his FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV32IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 8 regions + - 16 local interrupts signal that can be connected to off core complex devices + - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels + - GPIO memory with 16 interrupt lines + - SPI memory with 1 intterupt line + - Serial port with 1 interrupt line + - 1 RGB LEDS -- cgit v1.2.3 From 2ee3eec227ca11e0355358aa553b4618fff50bd9 Mon Sep 17 00:00:00 2001 From: Kevin Mills Date: Tue, 26 Feb 2019 08:02:01 -0800 Subject: Add corrected formatting for bullet lists Markdown bullet lists should: (1) have a blank line before and after the list; (2) start each list item at the beginning of the line (no leading white-space) The markdown processor in Freedom Studio enforces these standards and does not render correctly otherwise. --- bsp/coreip-e20/README.md | 7 ++++--- bsp/coreip-e21/README.md | 7 ++++--- bsp/coreip-e31-arty/README.md | 22 +++++++++++----------- bsp/coreip-e31/README.md | 12 ++++++------ bsp/coreip-s51-arty/README.md | 21 +++++++++++---------- bsp/coreip-s51/README.md | 11 ++++++----- bsp/sifive-hifive1/README.md | 19 ++++++++++--------- 7 files changed, 52 insertions(+), 47 deletions(-) diff --git a/bsp/coreip-e20/README.md b/bsp/coreip-e20/README.md index 5e19221..4c9fe1a 100644 --- a/bsp/coreip-e20/README.md +++ b/bsp/coreip-e20/README.md @@ -1,6 +1,7 @@ The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines. This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV32IMC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 4 regions + +- 1 hart with RV32IMC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 4 regions diff --git a/bsp/coreip-e21/README.md b/bsp/coreip-e21/README.md index 31719b3..a2f1a61 100644 --- a/bsp/coreip-e21/README.md +++ b/bsp/coreip-e21/README.md @@ -1,6 +1,7 @@ The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements. This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV32IMAC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 4 regions + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 4 regions diff --git a/bsp/coreip-e31-arty/README.md b/bsp/coreip-e31-arty/README.md index 1ae8739..eeb3502 100644 --- a/bsp/coreip-e31-arty/README.md +++ b/bsp/coreip-e31-arty/README.md @@ -1,14 +1,14 @@ The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV32IMAC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 8 regions - - 16 local interrupts signal that can be connected to off core complex devices - - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - - GPIO memory with 16 interrupt lines - - SPI memory with 1 intterupt line - - Serial port with 1 interrupt line - - 4 RGB LEDS - - 4 Buttons and 4 Switches -~ + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 intterupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches diff --git a/bsp/coreip-e31/README.md b/bsp/coreip-e31/README.md index 02f7723..ebfe371 100644 --- a/bsp/coreip-e31/README.md +++ b/bsp/coreip-e31/README.md @@ -1,9 +1,9 @@ The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV32IMAC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 8 regions - - 16 local interrupts signal that can be connected to off core complex devices - - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels -~ + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels diff --git a/bsp/coreip-s51-arty/README.md b/bsp/coreip-s51-arty/README.md index 6d6c04f..be9d317 100644 --- a/bsp/coreip-s51-arty/README.md +++ b/bsp/coreip-s51-arty/README.md @@ -1,13 +1,14 @@ The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV64IMAC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 8 regions - - 16 local interrupts signal that can be connected to off core complex devices - - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - - GPIO memory with 16 interrupt lines - - SPI memory with 1 intterupt line - - Serial port with 1 interrupt line - - 4 RGB LEDS - - 4 Buttons and 4 Switches + +- 1 hart with RV64IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 intterupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md index 3aa021f..a640a47 100644 --- a/bsp/coreip-s51/README.md +++ b/bsp/coreip-s51/README.md @@ -1,8 +1,9 @@ The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications. This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV64IMAC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 8 regions - - 16 local interrupts signal that can be connected to off core complex devices - - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels + +- 1 hart with RV64IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md index 1cc077e..faca2eb 100644 --- a/bsp/sifive-hifive1/README.md +++ b/bsp/sifive-hifive1/README.md @@ -1,12 +1,13 @@ HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications. his FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV32IMAC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 8 regions - - 16 local interrupts signal that can be connected to off core complex devices - - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - - GPIO memory with 16 interrupt lines - - SPI memory with 1 intterupt line - - Serial port with 1 interrupt line - - 1 RGB LEDS + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 intterupt line +- Serial port with 1 interrupt line +- 1 RGB LEDS -- cgit v1.2.3 From 01767ffd966798887ea3719fd51adb8c606710e8 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Wed, 27 Feb 2019 14:50:43 -0800 Subject: Optimize for size using gc-sections, function-sections, data-sections flags --- scripts/libmetal.mk | 2 +- scripts/standalone.mk | 6 +++--- 2 files changed, 4 insertions(+), 4 deletions(-) diff --git a/scripts/libmetal.mk b/scripts/libmetal.mk index 7cdb7c5..ea16632 100644 --- a/scripts/libmetal.mk +++ b/scripts/libmetal.mk @@ -13,7 +13,7 @@ $(BSP_DIR)/build/Makefile: @rm -rf $(dir $@) @mkdir -p $(dir $@) cd $(dir $@) && \ - CFLAGS="-march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -g -mcmodel=medany" \ + CFLAGS="-march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -ffunction-sections -fdata-sections -g -mcmodel=medany" \ $(abspath $(MEE_SOURCE_PATH)/configure) \ --host=$(CROSS_COMPILE) \ --prefix=$(abspath $(BSP_DIR)/install) \ diff --git a/scripts/standalone.mk b/scripts/standalone.mk index 52926ac..a412710 100644 --- a/scripts/standalone.mk +++ b/scripts/standalone.mk @@ -90,10 +90,10 @@ $(PROGRAM_ELF): \ AR=$(RISCV_AR) \ CC=$(RISCV_GCC) \ CXX=$(RISCV_GXX) \ - CFLAGS="-Os -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -g -mcmodel=medany -I$(abspath $(BSP_DIR)/install/include/)" \ - CXXFLAGS="-Os -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -g -mcmodel=medany -I$(abspath $(BSP_DIR)/install/include/)" \ + CFLAGS="-Os -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -ffunction-sections -fdata-sections -g -mcmodel=medany -I$(abspath $(BSP_DIR)/install/include/)" \ + CXXFLAGS="-Os -march=$(RISCV_ARCH) -mabi=$(RISCV_ABI) -ffunction-sections -fdata-sections -g -mcmodel=medany -I$(abspath $(BSP_DIR)/install/include/)" \ LDFLAGS="-nostartfiles -nostdlib -L$(sort $(dir $(abspath $(filter %.a,$^)))) -T$(abspath $(filter %.lds,$^))" \ - LDLIBS="-Wl,--start-group -lc -lgcc -lmetal -lmetal-gloss -Wl,--end-group" + LDLIBS="-Wl,--gc-sections -Wl,--start-group -lc -lgcc -lmetal -lmetal-gloss -Wl,--end-group" touch -c $@ .PHONY: clean-software -- cgit v1.2.3 From cbda1f5070e04de7ed3770d5dfd2e4f9abfc84b0 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Wed, 27 Feb 2019 15:46:57 -0800 Subject: Spellcheck correction readme for bsp targets for E20, E21, E31/Arty, S51/Arty --- bsp/coreip-e20/README.md | 1 - bsp/coreip-e31-arty/README.md | 6 +++--- bsp/coreip-e31/README.md | 2 +- bsp/coreip-s51-arty/README.md | 6 +++--- bsp/coreip-s51/README.md | 2 +- bsp/sifive-hifive1/README.md | 6 +++--- 6 files changed, 11 insertions(+), 12 deletions(-) diff --git a/bsp/coreip-e20/README.md b/bsp/coreip-e20/README.md index 4c9fe1a..f908327 100644 --- a/bsp/coreip-e20/README.md +++ b/bsp/coreip-e20/README.md @@ -4,4 +4,3 @@ This core target is suitable with Verilog RTL for verification and running appli - 1 hart with RV32IMC core - 4 hardware breakpoints -- Physical Mempory Protectin with 4 regions diff --git a/bsp/coreip-e31-arty/README.md b/bsp/coreip-e31-arty/README.md index eeb3502..c6558cb 100644 --- a/bsp/coreip-e31-arty/README.md +++ b/bsp/coreip-e31-arty/README.md @@ -1,14 +1,14 @@ The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. -This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines -- SPI memory with 1 intterupt line +- SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 4 RGB LEDS - 4 Buttons and 4 Switches diff --git a/bsp/coreip-e31/README.md b/bsp/coreip-e31/README.md index ebfe371..324369d 100644 --- a/bsp/coreip-e31/README.md +++ b/bsp/coreip-e31/README.md @@ -4,6 +4,6 @@ This core target is suitable with Verilog RTL for verification and running appli - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels diff --git a/bsp/coreip-s51-arty/README.md b/bsp/coreip-s51-arty/README.md index be9d317..0290171 100644 --- a/bsp/coreip-s51-arty/README.md +++ b/bsp/coreip-s51-arty/README.md @@ -1,14 +1,14 @@ The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications -This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: - 1 hart with RV64IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines -- SPI memory with 1 intterupt line +- SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 4 RGB LEDS - 4 Buttons and 4 Switches diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md index a640a47..60f75bf 100644 --- a/bsp/coreip-s51/README.md +++ b/bsp/coreip-s51/README.md @@ -4,6 +4,6 @@ This core target is suitable with Verilog RTL for verification and running appli - 1 hart with RV64IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels diff --git a/bsp/sifive-hifive1/README.md b/bsp/sifive-hifive1/README.md index faca2eb..6311207 100644 --- a/bsp/sifive-hifive1/README.md +++ b/bsp/sifive-hifive1/README.md @@ -1,13 +1,13 @@ HiFive1 is a low-cost, Arduino-compatible development board featuring the Freedom E310. It’s the best way to start prototyping and developing your RISC‑V applications. -his FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: +This target is ideal for getting familiarize with RISC-V ISA instructions set and freedom-metal libraries. It supports: - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines -- SPI memory with 1 intterupt line +- SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 1 RGB LEDS -- cgit v1.2.3