From 6cebe81ad76bd44d71297b5ec19fef0b9a01817f Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Sun, 8 Jul 2018 18:02:20 -0500 Subject: FS projects --- .../E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg | 31 ++++++++++++++++++++++ 1 file changed, 31 insertions(+) create mode 100644 FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg (limited to 'FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg') diff --git a/FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg b/FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg new file mode 100644 index 0000000..8b382dc --- /dev/null +++ b/FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" -- cgit v1.2.1-18-gbd029