From 0e8ad666d4d103ff1ee01118370ba837b8ad2fd4 Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Fri, 5 May 2017 12:42:58 -0500 Subject: Adding E31FPGA projects --- FreedomStudio/E31FPGA/demo_gpio/.cproject | 160 +++++++++ FreedomStudio/E31FPGA/demo_gpio/.gitignore | 1 + FreedomStudio/E31FPGA/demo_gpio/.project | 228 +++++++++++++ .../E31FPGA/demo_gpio/demo_gpio OpenOCD.launch | 59 ++++ FreedomStudio/E31FPGA/demo_gpio/link.lds | 167 ++++++++++ FreedomStudio/E31FPGA/demo_gpio/openocd.cfg | 31 ++ FreedomStudio/E31FPGA/global_interrupts/.cproject | 164 ++++++++++ FreedomStudio/E31FPGA/global_interrupts/.gitignore | 1 + FreedomStudio/E31FPGA/global_interrupts/.project | 363 +++++++++++++++++++++ .../global_interrupts Debug.launch | 59 ++++ .../E31FPGA/global_interrupts/global_interrupts.c | 250 ++++++++++++++ FreedomStudio/E31FPGA/global_interrupts/link.lds | 167 ++++++++++ .../E31FPGA/global_interrupts/openocd.cfg | 31 ++ FreedomStudio/E31FPGA/wrap-E31FPGA/.cproject | 134 ++++++++ FreedomStudio/E31FPGA/wrap-E31FPGA/.gitignore | 1 + FreedomStudio/E31FPGA/wrap-E31FPGA/.project | 153 +++++++++ 16 files changed, 1969 insertions(+) create mode 100644 FreedomStudio/E31FPGA/demo_gpio/.cproject create mode 100644 FreedomStudio/E31FPGA/demo_gpio/.gitignore create mode 100644 FreedomStudio/E31FPGA/demo_gpio/.project create mode 100644 FreedomStudio/E31FPGA/demo_gpio/demo_gpio OpenOCD.launch create mode 100644 FreedomStudio/E31FPGA/demo_gpio/link.lds create mode 100644 FreedomStudio/E31FPGA/demo_gpio/openocd.cfg create mode 100644 FreedomStudio/E31FPGA/global_interrupts/.cproject create mode 100644 FreedomStudio/E31FPGA/global_interrupts/.gitignore create mode 100644 FreedomStudio/E31FPGA/global_interrupts/.project create mode 100644 FreedomStudio/E31FPGA/global_interrupts/global_interrupts Debug.launch create mode 100644 FreedomStudio/E31FPGA/global_interrupts/global_interrupts.c create mode 100644 FreedomStudio/E31FPGA/global_interrupts/link.lds create mode 100644 FreedomStudio/E31FPGA/global_interrupts/openocd.cfg create mode 100644 FreedomStudio/E31FPGA/wrap-E31FPGA/.cproject create mode 100644 FreedomStudio/E31FPGA/wrap-E31FPGA/.gitignore create mode 100644 FreedomStudio/E31FPGA/wrap-E31FPGA/.project (limited to 'FreedomStudio/E31FPGA') diff --git a/FreedomStudio/E31FPGA/demo_gpio/.cproject b/FreedomStudio/E31FPGA/demo_gpio/.cproject new file mode 100644 index 0000000..cee272f --- /dev/null +++ b/FreedomStudio/E31FPGA/demo_gpio/.cproject @@ -0,0 +1,160 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreedomStudio/E31FPGA/demo_gpio/.gitignore b/FreedomStudio/E31FPGA/demo_gpio/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/FreedomStudio/E31FPGA/demo_gpio/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/FreedomStudio/E31FPGA/demo_gpio/.project b/FreedomStudio/E31FPGA/demo_gpio/.project new file mode 100644 index 0000000..5f5a4f9 --- /dev/null +++ b/FreedomStudio/E31FPGA/demo_gpio/.project @@ -0,0 +1,228 @@ + + + demo_gpio + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + bsp + 2 + virtual:/virtual + + + demo_gpio.c + 1 + PARENT-3-PROJECT_LOC/software/demo_gpio/demo_gpio.c + + + bsp/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/.DS_Store + + + bsp/drivers + 2 + virtual:/virtual + + + bsp/env + 2 + virtual:/virtual + + + bsp/include + 2 + virtual:/virtual + + + bsp/drivers/fe300prci + 2 + virtual:/virtual + + + bsp/drivers/plic + 2 + virtual:/virtual + + + bsp/env/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/env/.DS_Store + + + bsp/env/coreplexip-e31-arty + 2 + virtual:/virtual + + + bsp/env/encoding.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/encoding.h + + + bsp/env/entry.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/entry.S + + + bsp/env/hifive1.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/hifive1.h + + + bsp/env/start.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/start.S + + + bsp/include/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/include/.DS_Store + + + bsp/include/sifive + 2 + virtual:/virtual + + + bsp/drivers/fe300prci/fe300prci_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c + + + bsp/drivers/fe300prci/fe300prci_driver.h + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.h + + + bsp/drivers/plic/plic_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.c + + + bsp/drivers/plic/plic_driver.h + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.h + + + bsp/env/coreplexip-e31-arty/init.c + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/init.c + + + bsp/env/coreplexip-e31-arty/link.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/link.lds + + + bsp/env/coreplexip-e31-arty/openocd.cfg + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/openocd.cfg + + + bsp/env/coreplexip-e31-arty/platform.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/platform.h + + + bsp/env/coreplexip-e31-arty/settings.mk + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/settings.mk + + + bsp/include/sifive/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/.DS_Store + + + bsp/include/sifive/bits.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h + + + bsp/include/sifive/const.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h + + + bsp/include/sifive/devices + 2 + virtual:/virtual + + + bsp/include/sifive/sections.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h + + + bsp/include/sifive/smp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h + + + bsp/include/sifive/devices/aon.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h + + + bsp/include/sifive/devices/clint.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h + + + bsp/include/sifive/devices/gpio.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h + + + bsp/include/sifive/devices/otp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h + + + bsp/include/sifive/devices/plic.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h + + + bsp/include/sifive/devices/prci.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h + + + bsp/include/sifive/devices/pwm.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h + + + bsp/include/sifive/devices/spi.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h + + + bsp/include/sifive/devices/uart.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h + + + diff --git a/FreedomStudio/E31FPGA/demo_gpio/demo_gpio OpenOCD.launch b/FreedomStudio/E31FPGA/demo_gpio/demo_gpio OpenOCD.launch new file mode 100644 index 0000000..1e7b0d5 --- /dev/null +++ b/FreedomStudio/E31FPGA/demo_gpio/demo_gpio OpenOCD.launch @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreedomStudio/E31FPGA/demo_gpio/link.lds b/FreedomStudio/E31FPGA/demo_gpio/link.lds new file mode 100644 index 0000000..45a82d7 --- /dev/null +++ b/FreedomStudio/E31FPGA/demo_gpio/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/FreedomStudio/E31FPGA/demo_gpio/openocd.cfg b/FreedomStudio/E31FPGA/demo_gpio/openocd.cfg new file mode 100644 index 0000000..8b382dc --- /dev/null +++ b/FreedomStudio/E31FPGA/demo_gpio/openocd.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/FreedomStudio/E31FPGA/global_interrupts/.cproject b/FreedomStudio/E31FPGA/global_interrupts/.cproject new file mode 100644 index 0000000..2dd3494 --- /dev/null +++ b/FreedomStudio/E31FPGA/global_interrupts/.cproject @@ -0,0 +1,164 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreedomStudio/E31FPGA/global_interrupts/.gitignore b/FreedomStudio/E31FPGA/global_interrupts/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/FreedomStudio/E31FPGA/global_interrupts/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/FreedomStudio/E31FPGA/global_interrupts/.project b/FreedomStudio/E31FPGA/global_interrupts/.project new file mode 100644 index 0000000..6335740 --- /dev/null +++ b/FreedomStudio/E31FPGA/global_interrupts/.project @@ -0,0 +1,363 @@ + + + global_interrupts + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + bsp + 2 + virtual:/virtual + + + bsp/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/.DS_Store + + + bsp/drivers + 2 + virtual:/virtual + + + bsp/env + 2 + virtual:/virtual + + + bsp/include + 2 + virtual:/virtual + + + bsp/libwrap + 2 + virtual:/virtual + + + bsp/drivers/fe300prci + 2 + virtual:/virtual + + + bsp/drivers/plic + 2 + virtual:/virtual + + + bsp/env/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/env/.DS_Store + + + bsp/env/coreplexip-arty.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h + + + bsp/env/coreplexip-e31-arty + 2 + virtual:/virtual + + + bsp/env/encoding.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/encoding.h + + + bsp/env/entry.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/entry.S + + + bsp/env/hifive1.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/hifive1.h + + + bsp/env/start.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/start.S + + + bsp/include/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/include/.DS_Store + + + bsp/include/sifive + 2 + virtual:/virtual + + + bsp/libwrap/libwrap.mk + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/libwrap.mk + + + bsp/libwrap/misc + 2 + virtual:/virtual + + + bsp/libwrap/stdlib + 2 + virtual:/virtual + + + bsp/libwrap/sys + 2 + virtual:/virtual + + + bsp/drivers/fe300prci/fe300prci_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c + + + bsp/drivers/fe300prci/fe300prci_driver.h + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.h + + + bsp/drivers/plic/plic_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.c + + + bsp/drivers/plic/plic_driver.h + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.h + + + bsp/env/coreplexip-e31-arty/init.c + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/init.c + + + bsp/env/coreplexip-e31-arty/link.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/link.lds + + + bsp/env/coreplexip-e31-arty/openocd.cfg + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/openocd.cfg + + + bsp/env/coreplexip-e31-arty/platform.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/platform.h + + + bsp/env/coreplexip-e31-arty/settings.mk + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e31-arty/settings.mk + + + bsp/include/sifive/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/.DS_Store + + + bsp/include/sifive/bits.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h + + + bsp/include/sifive/const.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h + + + bsp/include/sifive/devices + 2 + virtual:/virtual + + + bsp/include/sifive/sections.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h + + + bsp/include/sifive/smp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h + + + bsp/libwrap/misc/write_hex.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c + + + bsp/libwrap/stdlib/malloc.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c + + + bsp/libwrap/sys/_exit.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c + + + bsp/libwrap/sys/close.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c + + + bsp/libwrap/sys/execve.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c + + + bsp/libwrap/sys/fork.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c + + + bsp/libwrap/sys/fstat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c + + + bsp/libwrap/sys/getpid.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c + + + bsp/libwrap/sys/isatty.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c + + + bsp/libwrap/sys/kill.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c + + + bsp/libwrap/sys/link.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c + + + bsp/libwrap/sys/lseek.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c + + + bsp/libwrap/sys/open.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c + + + bsp/libwrap/sys/openat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c + + + bsp/libwrap/sys/read.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c + + + bsp/libwrap/sys/sbrk.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c + + + bsp/libwrap/sys/stat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c + + + bsp/libwrap/sys/stub.h + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h + + + bsp/libwrap/sys/times.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c + + + bsp/libwrap/sys/unlink.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c + + + bsp/libwrap/sys/wait.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c + + + bsp/libwrap/sys/write.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c + + + bsp/include/sifive/devices/aon.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h + + + bsp/include/sifive/devices/clint.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h + + + bsp/include/sifive/devices/gpio.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h + + + bsp/include/sifive/devices/otp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h + + + bsp/include/sifive/devices/plic.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h + + + bsp/include/sifive/devices/prci.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h + + + bsp/include/sifive/devices/pwm.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h + + + bsp/include/sifive/devices/spi.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h + + + bsp/include/sifive/devices/uart.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h + + + diff --git a/FreedomStudio/E31FPGA/global_interrupts/global_interrupts Debug.launch b/FreedomStudio/E31FPGA/global_interrupts/global_interrupts Debug.launch new file mode 100644 index 0000000..f03bed5 --- /dev/null +++ b/FreedomStudio/E31FPGA/global_interrupts/global_interrupts Debug.launch @@ -0,0 +1,59 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreedomStudio/E31FPGA/global_interrupts/global_interrupts.c b/FreedomStudio/E31FPGA/global_interrupts/global_interrupts.c new file mode 100644 index 0000000..4d3a554 --- /dev/null +++ b/FreedomStudio/E31FPGA/global_interrupts/global_interrupts.c @@ -0,0 +1,250 @@ +// See LICENSE for license details. + +#include +#include +#include "platform.h" +#include +#include "plic/plic_driver.h" +#include "encoding.h" +#include + +#ifndef _SIFIVE_COREPLEXIP_ARTY_H +#error 'global_interrupts' demo only supported for Coreplex IP Eval Kits +#endif + +// Global Instance data for the PLIC +// for use by the PLIC Driver. +plic_instance_t g_plic; + +// Flag for state +int g_switch1Wins; + +// Debounce counter (PWM can't go slow enough) +int g_debounce; + +void debounce(); + +// Structures for registering different interrupt handlers +// for different parts of the application. +typedef void (*interrupt_function_ptr_t) (void); + +// See bsp/env//init.c for how this +// interrupt vector is used. +interrupt_function_ptr_t localISR[32]; + +interrupt_function_ptr_t g_ext_interrupt_handlers[PLIC_NUM_INTERRUPTS]; + +void set_timer() { + + volatile uint64_t * mtime = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIME); + volatile uint64_t * mtimecmp = (uint64_t*) (CLINT_CTRL_ADDR + CLINT_MTIMECMP); + uint64_t now = *mtime; + uint64_t then = now + 10*RTC_FREQ; + *mtimecmp = then; + +} + +/*Entry Point for Machine Timer Interrupt Handler*/ +void mti_isr(){ + + if (g_switch1Wins) { + printf("#### Giving Switch 1 Priority for 10 seconds ####\n"); + // All other things being equal, lower IDs have + // higher priority. We have already set + // Switch 1 to priority 2 + // in the setup, so by giving these equal priority Switch 1 will win. + PLIC_set_priority(&g_plic, INT_EXT_DEVICE_SW_2, 2); + } else { + printf("**** Giving Switch 2 Priority for 10 seconds ****\n"); + // By setting Switch 2 a higher integer priority, it will win over switch 1. + PLIC_set_priority(&g_plic, INT_EXT_DEVICE_SW_2, 3); + } + g_switch1Wins ^= 0x1; + + set_timer(); + +} + +/*Entry Point for PLIC Interrupt Handler*/ +void mei_isr(){ + plic_source int_num = PLIC_claim_interrupt(&g_plic); + if ((int_num >=1 ) && (int_num < PLIC_NUM_INTERRUPTS)) { + g_ext_interrupt_handlers[int_num](); + } + else { + exit(1 + (uintptr_t) int_num); + } + PLIC_complete_interrupt(&g_plic, int_num); +} + +const char * instructions_msg = " \ +\n\ + SIFIVE, INC.\n\ +E31/E51 Coreplex IP Eval Kit 'global_interrupts' demo.\n\ +\n\ +Switches 1 and 2 are enabled as External Global Interrupts \n\ +(they don't go through the PLIC). You an observe priorities.\n\ +Priorities invert every few seconds, which is driven by the \n\ +PWM0 global interrupt. \n\ +\n"; + +void print_instructions() { + + write (STDOUT_FILENO, instructions_msg, strlen(instructions_msg)); + +} + +void invalid_global_isr() { + printf("Unexpected global interrupt!\n"); +} + +void invalid_local_isr() { + printf ("Unexpected local interrupt!\n"); +} + +void switch_1_handler() { + + printf("Switch 1 is on! Even if Switch 2 is on, Switch 1 must have higher priority right now.\n"); + + // Set Green LED + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << GREEN_LED_OFFSET) ; + GPIO_REG(GPIO_OUTPUT_VAL) &= ~((0x1<< RED_LED_OFFSET)); + + debounce(); + +} + +void switch_2_handler() { + printf("Switch 2 is on! Even if Switch 1 is on, Switch 2 must have higher priority right now.\n"); + + // Set RED LED + GPIO_REG(GPIO_OUTPUT_VAL) &= ~(0x1 << GREEN_LED_OFFSET) ; + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1<< RED_LED_OFFSET); + + debounce(); +} + +// We use PWM 0 as a +// timer interrupt for debouncing. + +void pwm_0_handler() { + + + if (g_debounce == 0) { + printf(" Done debouncing.\n"); + + //Lower the threshold s.t. the switches can hit. + PLIC_set_threshold(&g_plic, 1); + + // Clear the PWM interrupt + PWM0_REG(PWM_CFG) = 0; + + } else { + // Keep waiting + g_debounce --; + // This clears out the interrupt and re-arms the timer. + PWM0_REG(PWM_CFG) = ((PWM_CFG_ONESHOT) | (PWM_CFG_ZEROCMP)| 0x7 | (PWM_CFG_STICKY)); + + } + +} + +void debounce(int local_interrupt_num) { + + printf(" Starting a debounce.\n"); + + g_debounce = 600; + + // This clears out the interrupt and re-arms the timer. + PWM0_REG(PWM_CFG) = ((PWM_CFG_ONESHOT) | (PWM_CFG_ZEROCMP)| 0x7 | (PWM_CFG_STICKY)); + + // Set the threshold high enough that the + // switches won't cause the interrupt to fire, + // only the PWM or timer interrupts. + PLIC_set_threshold(&g_plic, 4); + +} + +int main(int argc, char **argv) +{ + + for (int gisr = 0; gisr < PLIC_NUM_INTERRUPTS; gisr++){ + g_ext_interrupt_handlers[PLIC_NUM_INTERRUPTS] = invalid_global_isr; + } + g_ext_interrupt_handlers[PWM0_INT_BASE + 0] = pwm_0_handler; + g_ext_interrupt_handlers[INT_EXT_DEVICE_SW_1] = switch_1_handler; + g_ext_interrupt_handlers[INT_EXT_DEVICE_SW_2] = switch_2_handler; + + for (int lisr = 0; lisr < 32; lisr++){ + localISR[lisr] = invalid_local_isr; + } + + localISR[IRQ_M_TIMER] = mti_isr; + localISR[IRQ_M_EXT] = mei_isr; + + print_instructions(); + + // Set up RGB LEDs for a visual. + + GPIO_REG(GPIO_OUTPUT_EN) |= ((0x1<< RED_LED_OFFSET)| (0x1<< GREEN_LED_OFFSET)); + GPIO_REG(GPIO_OUTPUT_VAL) |= (0x1 << GREEN_LED_OFFSET) ; + GPIO_REG(GPIO_OUTPUT_VAL) &= ~(0x1<< RED_LED_OFFSET); + + /************************************************************************** + * Set up the PLIC + * + *************************************************************************/ + PLIC_init(&g_plic, + PLIC_CTRL_ADDR, + PLIC_NUM_INTERRUPTS, + PLIC_NUM_PRIORITIES); + + /************************************************************************** + * Give Switch 1 and Switch 2 Equal priority of 2. + * + *************************************************************************/ + + PLIC_enable_interrupt (&g_plic, PWM0_INT_BASE + 0); + PLIC_enable_interrupt (&g_plic, INT_EXT_DEVICE_SW_1); + PLIC_enable_interrupt (&g_plic, INT_EXT_DEVICE_SW_2); + + // PWM always beats the switches, because we use it + // as a debouncer, and we lower the threshold + // to do so. + + PWM0_REG(PWM_CFG) = 0; + + // Make sure people aren't blinded by LEDs connected here. + PWM0_REG(PWM_CMP0) = 0xFE; + PWM0_REG(PWM_CMP1) = 0xFF; + PWM0_REG(PWM_CMP2) = 0xFF; + PWM0_REG(PWM_CMP3) = 0xFF; + PLIC_set_priority(&g_plic, PWM0_INT_BASE + 0 , 5); + + // Start the switches out at the same priority. Switch1 + // would win. + PLIC_set_priority(&g_plic, INT_EXT_DEVICE_SW_1, 2); + PLIC_set_priority(&g_plic, INT_EXT_DEVICE_SW_2, 2); + + // Set up machine timer interrupt. Every few seconds it + // will invert the switch priorities. + set_timer(); + + // Enable timer interrupts. + set_csr(mie, MIP_MTIP); + + // Enable Global (PLIC) interrupts. + set_csr(mie, MIP_MEIP); + + g_switch1Wins = 1; + + // Enable all interrupts + set_csr(mstatus, MSTATUS_MIE); + + while(1){ + asm volatile ("wfi"); + } + + return 0; + +} diff --git a/FreedomStudio/E31FPGA/global_interrupts/link.lds b/FreedomStudio/E31FPGA/global_interrupts/link.lds new file mode 100644 index 0000000..45a82d7 --- /dev/null +++ b/FreedomStudio/E31FPGA/global_interrupts/link.lds @@ -0,0 +1,167 @@ +OUTPUT_ARCH( "riscv" ) + +ENTRY( _start ) + +MEMORY +{ + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 16K +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 2K; + + .init : + { + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + . = ALIGN(4); + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + .fini_array : + { + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__fini_array_end = .); + } >flash AT>flash :flash + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + } >flash AT>flash :flash + + .dalign : + { + . = ALIGN(4); + PROVIDE( _data = . ); + } >ram AT>flash :ram_init + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + } >ram AT>flash :ram_init + + .srodata : + { + PROVIDE( _gp = . + 0x800 ); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + .sdata : + { + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + } >ram AT>flash :ram_init + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + + .stack ORIGIN(ram) + LENGTH(ram) - __stack_size : + { + PROVIDE( _heap_end = . ); + . = __stack_size; + PROVIDE( _sp = . ); + } >ram AT>ram :ram +} diff --git a/FreedomStudio/E31FPGA/global_interrupts/openocd.cfg b/FreedomStudio/E31FPGA/global_interrupts/openocd.cfg new file mode 100644 index 0000000..8b382dc --- /dev/null +++ b/FreedomStudio/E31FPGA/global_interrupts/openocd.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/FreedomStudio/E31FPGA/wrap-E31FPGA/.cproject b/FreedomStudio/E31FPGA/wrap-E31FPGA/.cproject new file mode 100644 index 0000000..5c8b71e --- /dev/null +++ b/FreedomStudio/E31FPGA/wrap-E31FPGA/.cproject @@ -0,0 +1,134 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreedomStudio/E31FPGA/wrap-E31FPGA/.gitignore b/FreedomStudio/E31FPGA/wrap-E31FPGA/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/FreedomStudio/E31FPGA/wrap-E31FPGA/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/FreedomStudio/E31FPGA/wrap-E31FPGA/.project b/FreedomStudio/E31FPGA/wrap-E31FPGA/.project new file mode 100644 index 0000000..47109aa --- /dev/null +++ b/FreedomStudio/E31FPGA/wrap-E31FPGA/.project @@ -0,0 +1,153 @@ + + + wrap-E31FPGA + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + misc + 2 + virtual:/virtual + + + stdlib + 2 + virtual:/virtual + + + sys + 2 + virtual:/virtual + + + misc/write_hex.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c + + + stdlib/malloc.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c + + + sys/_exit.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c + + + sys/close.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c + + + sys/execve.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c + + + sys/fork.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c + + + sys/fstat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c + + + sys/getpid.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c + + + sys/isatty.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c + + + sys/kill.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c + + + sys/link.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c + + + sys/lseek.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c + + + sys/open.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c + + + sys/openat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c + + + sys/read.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c + + + sys/sbrk.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c + + + sys/stat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c + + + sys/stub.h + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h + + + sys/times.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c + + + sys/unlink.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c + + + sys/wait.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c + + + sys/write.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c + + + -- cgit v1.2.3 From d99510aa4eece7dfe3c3fd599a3d561893a4f1b1 Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Fri, 5 May 2017 14:09:39 -0500 Subject: updated demo_gpio --- FreedomStudio/E31FPGA/demo_gpio/.cproject | 11 ++-- .../E31FPGA/demo_gpio/demo_gpio OpenOCD.launch | 59 ---------------------- FreedomStudio/E31FPGA/wrap-E31FPGA/.cproject | 6 ++- 3 files changed, 12 insertions(+), 64 deletions(-) delete mode 100644 FreedomStudio/E31FPGA/demo_gpio/demo_gpio OpenOCD.launch (limited to 'FreedomStudio/E31FPGA') diff --git a/FreedomStudio/E31FPGA/demo_gpio/.cproject b/FreedomStudio/E31FPGA/demo_gpio/.cproject index cee272f..552d11b 100644 --- a/FreedomStudio/E31FPGA/demo_gpio/.cproject +++ b/FreedomStudio/E31FPGA/demo_gpio/.cproject @@ -43,8 +43,13 @@ - +