From 85577efc8e73f76fa4b7d742ff362988f6b4baf1 Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Thu, 28 Dec 2017 11:27:48 -0600
Subject: project and debug launch updates for beta 3

---
 FreedomStudio/E51FPGA/coreplexip_welcome/.cproject |    2 +-
 .../coreplexip_welcome OpenOCD.launch              |    1 +
 .../E51FPGA/coreplexip_welcome/e51arty-xsvd.json   | 1230 ++++++++++++++++++++
 3 files changed, 1232 insertions(+), 1 deletion(-)
 create mode 100644 FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json

(limited to 'FreedomStudio/E51FPGA/coreplexip_welcome')

diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
index 514d098..94913a8 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
@@ -41,7 +41,7 @@
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply.1035081321" name="Multiply extension (RVM)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.multiply" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic.632559401" name="Atomic extension (RVA)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.atomic" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed.1722118225" name="Compressed extension (RVC)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.isa.compressed" useByScannerDiscovery="false" value="true" valueType="boolean"/>
-							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.lp64" valueType="enumerated"/>
+							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer.281117582" name="Integer ABI" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.abi.integer" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.abi.integer.lp64" valueType="enumerated"/>
 							<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.427474672" name="Code model" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel" useByScannerDiscovery="false" value="ilg.gnumcueclipse.managedbuild.cross.riscv.option.target.codemodel.any" valueType="enumerated"/>
 							<targetPlatform archList="all" binaryParser="org.eclipse.cdt.core.ELF" id="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform.2059749159" isAbstract="false" osList="all" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.targetPlatform"/>
 							<builder buildPath="${workspace_loc:/coreplexip_welcome}/Debug" id="ilg.gnumcueclipse.managedbuild.cross.riscv.builder.964786236" keepEnvironmentInBuildfile="false" managedBuildOn="true" name="Gnu Make Builder" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.builder"/>
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch b/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
index 81a28b7..af063ab 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch	
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch	
@@ -20,6 +20,7 @@
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherInitCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.otherRunCommands" value=""/>
 <stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.secondResetType" value="halt"/>
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.svdPath" value="${project_loc}/e51arty-xsvd.json"/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageFileName" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.imageOffset" value=""/>
 <stringAttribute key="org.eclipse.cdt.debug.gdbjtag.core.ipAddress" value="localhost"/>
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json b/FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json
new file mode 100644
index 0000000..aac7a77
--- /dev/null
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/e51arty-xsvd.json
@@ -0,0 +1,1230 @@
+{
+  "schemaVersion": "0.2.4",
+  "contentVersion": "0.2.0",
+  "headerVersion": "0.2.0",
+  "device": {
+    "e51arty": {
+      "displayName": "Core Complex E51 Arty",
+      "description": "SiFive’s E51 is a synthesised version of Core Complex E31 running on the Arty board.",
+      "supplier": {
+        "name": "sifive",
+        "id": "1",
+        "displayName": "SiFive",
+        "fullName": "SiFive, Inc.",
+        "contact": "info@sifive.com"
+      },
+      "busWidth": "64",
+      "resetMask": "all",
+      "resetValue": "0x0000000000000000",
+      "access": "rw",
+      "headerGuardPrefix": "SIFIVE_DEVICES_ARTY_E51_",
+      "headerTypePrefix": "sifive_e51arty_",
+      "headerInterruptPrefix": "sifive_e51arty_interrupt_global_",
+      "headerInterruptEnumPrefix": "riscv_interrupts_global_",
+      "revision": "r0p0",
+      "numInterrupts": "26",
+      "priorityBits": "3",
+      "regWidth": "32",
+      "cores": {
+        "e51": {
+          "harts": "1",
+          "isa": "RV64IMAC",
+          "isaVersion": "2.2",
+          "mpu": "pmp",
+          "mmu": "none",
+          "localInterrupts": {
+            "machine_software": {
+              "description": "Machine Software Interrupt",
+              "value": "3"
+            },
+            "machine_timer": {
+              "description": "Machine Timer Interrupt",
+              "value": "7"
+            },
+            "machine_ext": {
+              "description": "Machine External Interrupt",
+              "value": "11"
+            },
+            "0": {
+              "description": "Local Interrupt 0",
+              "value": "16"
+            },
+            "1": {
+              "description": "Local Interrupt 1",
+              "value": "17"
+            },
+            "2": {
+              "description": "Local Interrupt 2",
+              "value": "18"
+            },
+            "3": {
+              "description": "Local Interrupt 3",
+              "value": "19"
+            },
+            "4": {
+              "description": "Local Interrupt 4",
+              "value": "20"
+            },
+            "5": {
+              "description": "Local Interrupt 5",
+              "value": "21"
+            },
+            "6": {
+              "description": "Local Interrupt 6",
+              "value": "22"
+            },
+            "7": {
+              "description": "Local Interrupt 7",
+              "value": "23"
+            },
+            "8": {
+              "description": "Local Interrupt 8",
+              "value": "24"
+            },
+            "9": {
+              "description": "Local Interrupt 9",
+              "value": "25"
+            },
+            "10": {
+              "description": "Local Interrupt 10",
+              "value": "26"
+            },
+            "11": {
+              "description": "Local Interrupt 11",
+              "value": "27"
+            },
+            "12": {
+              "description": "Local Interrupt 12",
+              "value": "28"
+            },
+            "13": {
+              "description": "Local Interrupt 13",
+              "value": "29"
+            },
+            "14": {
+              "description": "Local Interrupt 14",
+              "value": "30"
+            },
+            "15": {
+              "description": "Local Interrupt 15",
+              "value": "31"
+            }
+          },
+          "numLocalInterrupts": "16"
+        }
+      },
+      "peripherals": {
+        "clint": {
+          "description": "Core Complex Local Interruptor (CLINT) Peripheral",
+          "baseAddress": "0x02000000",
+          "size": "0x10000",
+          "registers": {
+            "msip": {
+              "description": "MSIP (Machine-mode Software Interrupts) Register per Hart",
+              "addressOffset": "0x0000",
+              "arraySize": "1"
+            },
+            "mtimecmp": {
+              "description": "Machine Time Compare Registers per Hart",
+              "addressOffset": "0x4000",
+              "arraySize": "1",
+              "regWidth": "64"
+            },
+            "mtime": {
+              "description": "Machine Time Register",
+              "addressOffset": "0xBFF8",
+              "access": "r",
+              "regWidth": "64"
+            }
+          }
+        },
+        "plic": {
+          "description": "Platform-Level Interrupt Controller (PLIC) Peripheral",
+          "baseAddress": "0x0C000000",
+          "size": "0x4000000",
+          "registers": {
+            "priorities": {
+              "arraySize": "27",
+              "description": "Interrupt Priorities Registers; 0 is reserved.",
+              "addressOffset": "0x0000",
+              "fields": {
+                "value": {
+                  "description": "The priority for a given global interrupt",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "pendings": {
+              "arraySize": "16",
+              "description": "Interrupt Pending Bits Registers",
+              "addressOffset": "0x1000",
+              "access": "r"
+            }
+          },
+          "clusters": {
+            "enablestarget0": {
+              "description": "Hart 0 Interrupt Enable Bits",
+              "addressOffset": "0x00002000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-mode Interrupt Enable Bits",
+                  "registers": {
+                    "enables": {
+                      "arraySize": "16",
+                      "description": "Interrupt Enable Bits Registers",
+                      "addressOffset": "0x0000"
+                    }
+                  }
+                }
+              }
+            },
+            "target0": {
+              "description": "Hart 0 Interrupt Thresholds",
+              "addressOffset": "0x00200000",
+              "clusters": {
+                "m": {
+                  "addressOffset": "0x0000",
+                  "description": "Hart 0 M-Mode Interrupt Threshold",
+                  "registers": {
+                    "threshold": {
+                      "description": "The Priority Threshold Register",
+                      "addressOffset": "0x0000",
+                      "fields": {
+                        "value": {
+                          "description": "The priority threshold value",
+                          "bitOffset": "0",
+                          "bitWidth": "3",
+                          "resetMask": "all",
+                          "resetValue": "0x0"
+                        }
+                      }
+                    },
+                    "claimcomplete": {
+                      "description": "The Interrupt Claim/Completion Register",
+                      "addressOffset": "0x0004"
+                    }
+                  }
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "switch0": {
+              "description": "SWITCH 0 Interrupt",
+              "value": "2"
+            },
+            "switch1": {
+              "description": "SWITCH 1 Interrupt",
+              "value": "3"
+            },
+            "switch2": {
+              "description": "SWITCH 2 Interrupt",
+              "value": "4"
+            },
+            "switch3": {
+              "description": "SWITCH 3 Interrupt",
+              "value": "5"
+            }
+          }
+        },
+        "gpio": {
+          "description": "General Purpose Input/Output Controller (GPIO) Peripheral",
+          "baseAddress": "0x20002000",
+          "size": "0x1000",
+          "registers": {
+            "value": {
+              "description": "Pin Value Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "inputen": {
+              "description": "Pin Input Enable Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Input Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outputen": {
+              "description": "Pin Output Enable Register",
+              "addressOffset": "0x008",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Output Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "port": {
+              "description": "Output Port Value Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output Port Value Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "pue": {
+              "description": "Internal Pull-up Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Internal Pull-up Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "ds": {
+              "description": "Pin Drive Strength Register",
+              "addressOffset": "0x014",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Pin Drive Strength Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseie": {
+              "description": "Rise Interrupt Enable Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "riseip": {
+              "description": "Rise Interrupt Pending Register",
+              "addressOffset": "0x01C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Rise Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallie": {
+              "description": "Fall Interrupt Enable Register",
+              "addressOffset": "0x020",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "fallip": {
+              "description": "Fall Interrupt Pending Register",
+              "addressOffset": "0x024",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Fall Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highie": {
+              "description": "High Interrupt Enable Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "highip": {
+              "description": "High Interrupt Pending Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "High Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowie": {
+              "description": "Low Interrupt Enable Register",
+              "addressOffset": "0x030",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "lowip": {
+              "description": "Low Interrupt Pending Register",
+              "addressOffset": "0x034",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Low Interrupt Pending Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofen": {
+              "description": "HW I/O Function Enable Register",
+              "addressOffset": "0x038",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Enable Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "iofsel": {
+              "description": "HW I/O Function Select Register",
+              "addressOffset": "0x03C",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "HW I/O Function Select Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            },
+            "outxor": {
+              "description": "Output XOR (invert) Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "bit": {
+                  "repeatGenerator": "0-31",
+                  "description": "Output XOR Bit Field",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "headerName": ""
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "gpio0": {
+              "description": "GPIO0 Interrupt",
+              "value": "7"
+            },
+            "gpio1": {
+              "description": "GPIO1 Interrupt",
+              "value": "8"
+            },
+            "gpio2": {
+              "description": "GPIO2 Interrupt",
+              "value": "9"
+            },
+            "gpio3": {
+              "description": "GPIO3 Interrupt",
+              "value": "10"
+            },
+            "gpio4": {
+              "description": "GPIO4 Interrupt",
+              "value": "11"
+            },
+            "gpio5": {
+              "description": "GPIO5 Interrupt",
+              "value": "12"
+            },
+            "gpio6": {
+              "description": "GPIO6 Interrupt",
+              "value": "13"
+            },
+            "gpio7": {
+              "description": "GPIO7 Interrupt",
+              "value": "14"
+            },
+            "gpio8": {
+              "description": "GPIO8 Interrupt",
+              "value": "15"
+            },
+            "gpio9": {
+              "description": "GPIO9 Interrupt",
+              "value": "16"
+            },
+            "gpio10": {
+              "description": "GPIO10 Interrupt",
+              "value": "17"
+            },
+            "gpio11": {
+              "description": "GPIO11 Interrupt",
+              "value": "18"
+            },
+            "gpio12": {
+              "description": "GPIO12 Interrupt",
+              "value": "19"
+            },
+            "gpio13": {
+              "description": "GPIO13 Interrupt",
+              "value": "20"
+            },
+            "gpio14": {
+              "description": "GPIO14 Interrupt",
+              "value": "21"
+            },
+            "gpio15": {
+              "description": "GPIO15 Interrupt",
+              "value": "22"
+            }
+          }
+        },
+        "uart0": {
+          "description": "Universal Asynchronous Receiver/Transmitter (UART) Peripheral",
+          "baseAddress": "0x20000000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "uart",
+          "registers": {
+            "txdata": {
+              "description": "Transmit Data Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "full": {
+                  "description": "Transmit FIFO full",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Receive Data Register",
+              "addressOffset": "0x004",
+              "resetMask": "none",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "access": "r"
+                },
+                "empty": {
+                  "description": "Receive FIFO empty",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txctrl": {
+              "description": "Transmit Control Register ",
+              "addressOffset": "0x008",
+              "fields": {
+                "txen": {
+                  "description": "Transmit enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "nstop": {
+                  "description": "Number of stop bits",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "txcnt": {
+                  "description": "Transmit watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "rxctrl": {
+              "description": "Receive Control Register",
+              "addressOffset": "0x00C",
+              "fields": {
+                "rxen": {
+                  "description": "Receive enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxcnt": {
+                  "description": "Receive watermark level",
+                  "bitOffset": "16",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x014",
+              "access": "r",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark interrupt pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1"
+                },
+                "rxwm": {
+                  "description": "Receive watermark interrupt pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "div": {
+              "description": "Baud Rate Divisor Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "value": {
+                  "description": "Baud rate divisor",
+                  "bitOffset": "0",
+                  "bitWidth": "16",
+                  "resetMask": "all",
+                  "resetValue": "0x0000FFFF"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "uart0": {
+              "description": "UART0 Interrupt",
+              "value": "1"
+            }
+          }
+        },
+        "spi0": {
+          "description": "Serial Peripheral Interface (SPI) Peripheral",
+          "baseAddress": "0x20004000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "spi",
+          "registers": {
+            "sckdiv": {
+              "description": "Serial clock divisor Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Divisor for serial clock",
+                  "bitOffset": "0",
+                  "bitWidth": "12",
+                  "resetMask": "all",
+                  "resetValue": "0x003"
+                }
+              }
+            },
+            "sckmode": {
+              "description": "Serial Clock Mode Register",
+              "addressOffset": "0x004",
+              "fields": {
+                "pha": {
+                  "description": "Serial clock phase",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "pol": {
+                  "description": "Serial clock polarity",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "csid": {
+              "description": "Chip Select ID Register",
+              "addressOffset": "0x010",
+              "resetMask": "all",
+              "resetValue": "0x00000000"
+            },
+            "csdef": {
+              "description": "Chip Select Default Register",
+              "addressOffset": "0x014",
+              "resetMask": "all",
+              "resetValue": "0x00000001"
+            },
+            "csmode": {
+              "description": "Chip Select Mode Register",
+              "addressOffset": "0x018",
+              "fields": {
+                "mode": {
+                  "description": "Chip select mode",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "csmode-enum": {
+                      "description": "Chip Select Modes Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "auto",
+                          "description": "Assert/de-assert CS at the beginning/end of each frame"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        },
+                        "2": {
+                          "displayName": "hold",
+                          "description": "Keep CS continuously asserted after the initial frame"
+                        },
+                        "3": {
+                          "displayName": "off",
+                          "description": "Disable hardware control of the CS pin"
+                        }
+                      }
+                    }
+                  }
+                }
+              }
+            },
+            "delay0": {
+              "description": "Delay Control 0 Register",
+              "addressOffset": "0x028",
+              "fields": {
+                "cssck": {
+                  "description": "CS to SCK Delay",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "sckcs": {
+                  "description": "SCK to CS Delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "delay1": {
+              "description": "Delay Control 1 Register",
+              "addressOffset": "0x02C",
+              "fields": {
+                "intercs": {
+                  "description": "Minimum CS inactive time",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                },
+                "interxfr": {
+                  "description": "Maximum interframe delay",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x01"
+                }
+              }
+            },
+            "fmt": {
+              "description": "Frame Format Register",
+              "addressOffset": "0x040",
+              "fields": {
+                "proto": {
+                  "description": "SPI Protocol",
+                  "bitOffset": "0",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "proto-enum": {
+                      "description": "SPI Protocol Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "single",
+                          "description": "DQ0 (MOSI), DQ1 (MISO)"
+                        },
+                        "1": {
+                          "displayName": "dual",
+                          "description": "DQ0, DQ1"
+                        },
+                        "2": {
+                          "displayName": "quad",
+                          "description": "DQ0, DQ1, DQ2, DQ3"
+                        },
+                        "*": {
+                          "displayName": "reserved"
+                        }
+                      }
+                    }
+                  }
+                },
+                "endian": {
+                  "description": "SPI endianness",
+                  "bitOffset": "2",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0",
+                  "enumerations": {
+                    "endian-enum": {
+                      "description": "SPI Endianness Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "msb",
+                          "description": "Transmit most-significant bit (MSB) first"
+                        },
+                        "1": {
+                          "displayName": "lsb",
+                          "description": "Transmit least-significant bit (LSB) first"
+                        }
+                      }
+                    }
+                  }
+                },
+                "dir": {
+                  "description": "SPI I/O Direction",
+                  "bitOffset": "3",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1",
+                  "enumerations": {
+                    "dir-enum": {
+                      "description": "SPI I/O Direction Enumeration",
+                      "values": {
+                        "0": {
+                          "displayName": "rx",
+                          "description": "For dual and quad protocols, the DQ pins are tri-stated. For the single protocol, the DQ0 pin is driven with the transmit data as normal."
+                        },
+                        "1": {
+                          "displayName": "tx",
+                          "description": "The receive FIFO is not populated."
+                        }
+                      }
+                    }
+                  }
+                },
+                "len": {
+                  "description": "Number of bits per frame",
+                  "bitOffset": "16",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x8"
+                }
+              }
+            },
+            "txdata": {
+              "description": "Tx FIFO Data Register",
+              "addressOffset": "0x048",
+              "fields": {
+                "data": {
+                  "description": "Transmit data",
+                  "bitOffset": "0",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x00"
+                },
+                "full": {
+                  "description": "FIFO full flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            },
+            "rxdata": {
+              "description": "Rx FIFO Data Register",
+              "addressOffset": "0x04C",
+              "resetMask": "none",
+              "access": "r",
+              "fields": {
+                "data": {
+                  "description": "Received data",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                },
+                "empty": {
+                  "description": "FIFO empty flag",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "txmark": {
+              "description": "Tx FIFO Watermark Register",
+              "addressOffset": "0x050",
+              "fields": {
+                "value": {
+                  "description": "Transmit watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "rxmark": {
+              "description": "Rx FIFO Watermark Register",
+              "addressOffset": "0x054",
+              "fields": {
+                "value": {
+                  "description": "Receive watermark",
+                  "bitOffset": "0",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "fctrl": {
+              "description": "Flash Interface Control Register",
+              "addressOffset": "0x060",
+              "fields": {
+                "en": {
+                  "description": "SPI Flash Mode Select",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                }
+              }
+            },
+            "ffmt": {
+              "description": "Flash Instruction Format Register",
+              "addressOffset": "0x064",
+              "fields": {
+                "cmden": {
+                  "description": "Enable sending of command",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x1"
+                },
+                "addrlen": {
+                  "description": "Number of address bytes(0 to 4)",
+                  "bitOffset": "1",
+                  "bitWidth": "3",
+                  "resetMask": "all",
+                  "resetValue": "0x3"
+                },
+                "padcnt": {
+                  "description": "Number of dummy cycles",
+                  "bitOffset": "4",
+                  "bitWidth": "4",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdproto": {
+                  "description": "Protocol for transmitting command",
+                  "bitOffset": "8",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "addrproto": {
+                  "description": "Protocol for transmitting address and padding",
+                  "bitOffset": "10",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "dataproto": {
+                  "description": "Protocol for receiving data bytes",
+                  "bitOffset": "12",
+                  "bitWidth": "2",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmdcode": {
+                  "description": "Value of command byte",
+                  "bitOffset": "16",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x03"
+                },
+                "padcode": {
+                  "description": "First 8 bits to transmit during dummy cycles",
+                  "bitOffset": "24",
+                  "bitWidth": "8",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ie": {
+              "description": "Interrupt Enable Register",
+              "addressOffset": "0x070",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark enable",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "rxwm": {
+                  "description": "Receive watermark enable",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                }
+              }
+            },
+            "ip": {
+              "description": "Interrupt Pending Register",
+              "addressOffset": "0x074",
+              "fields": {
+                "txwm": {
+                  "description": "Transmit watermark pending",
+                  "bitOffset": "0",
+                  "bitWidth": "1",
+                  "access": "r"
+                },
+                "rxwm": {
+                  "description": "Receive watermark pending",
+                  "bitOffset": "1",
+                  "bitWidth": "1",
+                  "access": "r"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "spi0": {
+              "description": "SPI0 Interrupt",
+              "value": "6"
+            }
+          }
+        },
+        "pwm0": {
+          "description": "Pulse-Width Modulation (PWM) Peripheral",
+          "baseAddress": "0x20005000",
+          "size": "0x1000",
+          "resetMask": "none",
+          "groupName": "pwm",
+          "registers": {
+            "cfg": {
+              "description": "Configuration Register",
+              "addressOffset": "0x000",
+              "fields": {
+                "scale": {
+                  "description": "Counter scale",
+                  "bitOffset": "0",
+                  "bitWidth": "4"
+                },
+                "sticky": {
+                  "description": "Sticky - disallow clearing pwmcmpXip bits",
+                  "bitOffset": "8",
+                  "bitWidth": "1"
+                },
+                "zerocmp": {
+                  "description": "Zero - counter resets to zero after match",
+                  "bitOffset": "9",
+                  "bitWidth": "1"
+                },
+                "deglitch": {
+                  "description": "Deglitch - latch pwmcmpXip within same cycle",
+                  "bitOffset": "10",
+                  "bitWidth": "1"
+                },
+                "enalways": {
+                  "description": "Enable always - run continuously",
+                  "bitOffset": "12",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "enoneshot": {
+                  "description": "enable one shot - run one cycle",
+                  "bitOffset": "13",
+                  "bitWidth": "1",
+                  "resetMask": "all",
+                  "resetValue": "0x0"
+                },
+                "cmp0center": {
+                  "description": "PWM0 Compare Center",
+                  "bitOffset": "16",
+                  "bitWidth": "1"
+                },
+                "cmp1center": {
+                  "description": "PWM1 Compare Center",
+                  "bitOffset": "17",
+                  "bitWidth": "1"
+                },
+                "cmp2center": {
+                  "description": "PWM2 Compare Center",
+                  "bitOffset": "18",
+                  "bitWidth": "1"
+                },
+                "cmp3center": {
+                  "description": "PWM3 Compare Center",
+                  "bitOffset": "19",
+                  "bitWidth": "1"
+                },
+                "cmp0gang": {
+                  "description": "PWM0/PWM1 Compare Gang",
+                  "bitOffset": "24",
+                  "bitWidth": "1"
+                },
+                "cmp1gang": {
+                  "description": "PWM1/PWM2 Compare Gang",
+                  "bitOffset": "25",
+                  "bitWidth": "1"
+                },
+                "cmp2gang": {
+                  "description": "PWM2/PWM3 Compare Gang",
+                  "bitOffset": "26",
+                  "bitWidth": "1"
+                },
+                "cmp3gang": {
+                  "description": "PWM3/PWM0 Compare Gang",
+                  "bitOffset": "27",
+                  "bitWidth": "1"
+                },
+                "cmp0ip": {
+                  "description": "PWM0 Interrupt Pending",
+                  "bitOffset": "28",
+                  "bitWidth": "1"
+                },
+                "cmp1ip": {
+                  "description": "PWM1 Interrupt Pending",
+                  "bitOffset": "29",
+                  "bitWidth": "1"
+                },
+                "cmp2ip": {
+                  "description": "PWM2 Interrupt Pending",
+                  "bitOffset": "30",
+                  "bitWidth": "1"
+                },
+                "cmp3ip": {
+                  "description": "PWM3 Interrupt Pending",
+                  "bitOffset": "31",
+                  "bitWidth": "1"
+                }
+              }
+            },
+            "count": {
+              "description": "Configuration Register",
+              "addressOffset": "0x008"
+            },
+            "scale": {
+              "description": "Scale Register",
+              "addressOffset": "0x010",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            },
+            "cmp": {
+              "arraySize": "4",
+              "description": "Compare Registers",
+              "addressOffset": "0x020",
+              "fields": {
+                "value": {
+                  "description": "Compare value",
+                  "bitOffset": "0",
+                  "bitWidth": "8"
+                }
+              }
+            }
+          },
+          "interrupts": {
+            "pwm0cmp0": {
+              "description": "PWM0 Compare 0 Interrupt",
+              "value": "23"
+            },
+            "pwm0cmp1": {
+              "description": "PWM0 Compare 1 Interrupt",
+              "value": "24"
+            },
+            "pwm0cmp2": {
+              "description": "PWM0 Compare 2 Interrupt",
+              "value": "25"
+            },
+            "pwm0cmp3": {
+              "description": "PWM0 Compare 3 Interrupt",
+              "value": "26"
+            }
+          }
+        }
+      }
+    }
+  }
+}
\ No newline at end of file
-- 
cgit v1.2.3


From dceeead112238a6f3e8475160155cc7b9d2a9265 Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Tue, 2 Jan 2018 14:37:39 -0600
Subject: updated project files

---
 FreedomStudio/E51FPGA/coreplexip_welcome/.cproject | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'FreedomStudio/E51FPGA/coreplexip_welcome')

diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
index 94913a8..d2588c4 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
@@ -89,10 +89,11 @@
 									<listOptionValue builtIn="false" value="../../wrap-E51FPGA/Debug"/>
 									<listOptionValue builtIn="false" value="../"/>
 								</option>
-								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit" valueType="string"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exi -Wl,--wrap=putst" valueType="string"/>
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1308651449" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/bsp/env/coreplexip-e51-arty/flash.lds}&quot;"/>
 								</option>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.221590263" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 								<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input.1622617219" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
-- 
cgit v1.2.3


From 58e6e3549940bd6d079dc6a7588cca3a2fff099a Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Wed, 3 Jan 2018 22:05:30 -0600
Subject: E31Arty FS project updates

---
 FreedomStudio/E51FPGA/coreplexip_welcome/.cproject | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'FreedomStudio/E51FPGA/coreplexip_welcome')

diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
index d2588c4..189a64e 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
@@ -89,7 +89,7 @@
 									<listOptionValue builtIn="false" value="../../wrap-E51FPGA/Debug"/>
 									<listOptionValue builtIn="false" value="../"/>
 								</option>
-								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exi -Wl,--wrap=putst" valueType="string"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit -Wl,--wrap=puts -Wl,--wrap=_malloc -Wl,--wrap=_free -Wl,--wrap=_open -Wl,--wrap=_lseek -Wl,--wrap=_read -Wl,--wrap=_write -Wl,--wrap=_fstat -Wl,--wrap=_stat -Wl,--wrap=_close -Wl,--wrap=_link -Wl,--wrap=_unlink -Wl,--wrap=_execve -Wl,--wrap=_fork -Wl,--wrap=_getpid -Wl,--wrap=_kill -Wl,--wrap=_wait -Wl,--wrap=_isatty -Wl,--wrap=_times -Wl,--wrap=_sbrk -Wl,--wrap=__exit -Wl,--wrap=_puts" valueType="string"/>
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1308651449" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/bsp/env/coreplexip-e51-arty/flash.lds}&quot;"/>
 								</option>
-- 
cgit v1.2.3


From 4212ec8feb64ac93699f504603e192a8d714a3d3 Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Wed, 3 Jan 2018 22:45:57 -0600
Subject: E51 FS project updates

---
 FreedomStudio/E51FPGA/coreplexip_welcome/.cproject |   4 +-
 FreedomStudio/E51FPGA/coreplexip_welcome/.project  | 160 +++++++++++++++++++++
 .../coreplexip_welcome OpenOCD.launch              |   1 +
 3 files changed, 162 insertions(+), 3 deletions(-)

(limited to 'FreedomStudio/E51FPGA/coreplexip_welcome')

diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
index 189a64e..2a42a43 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
@@ -83,17 +83,15 @@
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart.411410557" name="Do not use standard start files (-nostartfiles)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.nostart" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs.1839746398" name="Libraries (-l)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.libs" useByScannerDiscovery="false" valueType="libs">
 									<listOptionValue builtIn="false" value="c"/>
-									<listOptionValue builtIn="false" value="wrap-E51FPGA"/>
 								</option>
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths.1780520059" name="Library search path (-L)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.paths" useByScannerDiscovery="false" valueType="libPaths">
-									<listOptionValue builtIn="false" value="../../wrap-E51FPGA/Debug"/>
 									<listOptionValue builtIn="false" value="../"/>
 								</option>
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other.724386459" name="Other linker flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.other" useByScannerDiscovery="false" value="-Wl,--start-group -Wl,--end-group -Wl,--wrap=malloc -Wl,--wrap=free -Wl,--wrap=open -Wl,--wrap=lseek -Wl,--wrap=read -Wl,--wrap=write -Wl,--wrap=fstat -Wl,--wrap=stat -Wl,--wrap=close -Wl,--wrap=link -Wl,--wrap=unlink -Wl,--wrap=execve -Wl,--wrap=fork -Wl,--wrap=getpid -Wl,--wrap=kill -Wl,--wrap=wait -Wl,--wrap=isatty -Wl,--wrap=times -Wl,--wrap=sbrk -Wl,--wrap=_exit -Wl,--wrap=puts -Wl,--wrap=_malloc -Wl,--wrap=_free -Wl,--wrap=_open -Wl,--wrap=_lseek -Wl,--wrap=_read -Wl,--wrap=_write -Wl,--wrap=_fstat -Wl,--wrap=_stat -Wl,--wrap=_close -Wl,--wrap=_link -Wl,--wrap=_unlink -Wl,--wrap=_execve -Wl,--wrap=_fork -Wl,--wrap=_getpid -Wl,--wrap=_kill -Wl,--wrap=_wait -Wl,--wrap=_isatty -Wl,--wrap=_times -Wl,--wrap=_sbrk -Wl,--wrap=__exit -Wl,--wrap=_puts" valueType="string"/>
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile.1308651449" name="Script files (-T)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.scriptfile" useByScannerDiscovery="false" valueType="stringList">
 									<listOptionValue builtIn="false" value="&quot;${workspace_loc:/${ProjName}/bsp/env/coreplexip-e51-arty/flash.lds}&quot;"/>
 								</option>
-								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.221590263" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
+								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano.221590263" name="Use newlib-nano (--specs=nano.specs)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.linker.usenewlibnano" useByScannerDiscovery="false" value="true" valueType="boolean"/>
 								<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input.1622617219" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.c.linker.input">
 									<additionalInput kind="additionalinputdependency" paths="$(USER_OBJS)"/>
 									<additionalInput kind="additionalinput" paths="$(LIBS)"/>
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.project b/FreedomStudio/E51FPGA/coreplexip_welcome/.project
index 591c4d9..55ef108 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/.project
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/.project
@@ -54,6 +54,11 @@
 			<type>2</type>
 			<locationURI>virtual:/virtual</locationURI>
 		</link>
+		<link>
+			<name>bsp/libwrap</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
 		<link>
 			<name>bsp/drivers/.DS_Store</name>
 			<type>1</type>
@@ -114,6 +119,26 @@
 			<type>2</type>
 			<locationURI>virtual:/virtual</locationURI>
 		</link>
+		<link>
+			<name>bsp/libwrap/.DS_Store</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/.DS_Store</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/misc</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/stdlib</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys</name>
+			<type>2</type>
+			<locationURI>virtual:/virtual</locationURI>
+		</link>
 		<link>
 			<name>bsp/drivers/fe300prci/fe300prci_driver.c</name>
 			<type>1</type>
@@ -184,6 +209,141 @@
 			<type>1</type>
 			<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
 		</link>
+		<link>
+			<name>bsp/libwrap/misc/.DS_Store</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/.DS_Store</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/misc/write_hex.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/stdlib/.DS_Store</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/.DS_Store</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/stdlib/malloc.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/.DS_Store</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/.DS_Store</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/_exit.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/close.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/execve.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/fork.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/fstat.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/getpid.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/isatty.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/kill.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/link.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/lseek.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/open.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/openat.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/puts.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/read.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/sbrk.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/stat.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/stub.h</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/times.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/unlink.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/wait.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/weak_under_alias.h</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h</locationURI>
+		</link>
+		<link>
+			<name>bsp/libwrap/sys/write.c</name>
+			<type>1</type>
+			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c</locationURI>
+		</link>
 		<link>
 			<name>bsp/include/sifive/devices/aon.h</name>
 			<type>1</type>
diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch b/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch
index af063ab..9d170a8 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch	
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/coreplexip_welcome OpenOCD.launch	
@@ -1,5 +1,6 @@
 <?xml version="1.0" encoding="UTF-8" standalone="no"?>
 <launchConfiguration type="ilg.gnumcueclipse.debug.gdbjtag.openocd.launchConfigurationType">
+<stringAttribute key="ilg.gnumcueclipse.debug.gdbjtag.PERIPHERALS" value="&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot; standalone=&quot;no&quot;?&gt;&#10;&lt;peripherals&gt;&#10;&lt;peripheral name=&quot;gpio&quot;/&gt;&#10;&lt;/peripherals&gt;&#10;"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doContinue" value="true"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doDebugInRam" value="false"/>
 <booleanAttribute key="ilg.gnumcueclipse.debug.gdbjtag.openocd.doFirstReset" value="true"/>
-- 
cgit v1.2.3


From a41bda1c30485cf938db2e8750b2768ae04d2851 Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Thu, 4 Jan 2018 17:01:39 -0600
Subject: remove duplicated paths

---
 FreedomStudio/E51FPGA/coreplexip_welcome/.cproject | 8 --------
 1 file changed, 8 deletions(-)

(limited to 'FreedomStudio/E51FPGA/coreplexip_welcome')

diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
index 2a42a43..7da94d5 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/.cproject
@@ -52,10 +52,6 @@
 									<listOptionValue builtIn="false" value="../../../../bsp/env"/>
 									<listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
 									<listOptionValue builtIn="false" value="../../../../bsp/drivers"/>
-									<listOptionValue builtIn="false" value="../bsp/drivers"/>
-									<listOptionValue builtIn="false" value="../bsp/env"/>
-									<listOptionValue builtIn="false" value="../bsp/env/coreplexip-e51-arty"/>
-									<listOptionValue builtIn="false" value="../bsp/include"/>
 								</option>
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other.1801720442" name="Other assembler flags" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.assembler.other" useByScannerDiscovery="false" value="-c" valueType="string"/>
 								<inputType id="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input.31099272" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.tool.assembler.input"/>
@@ -65,10 +61,6 @@
 									<listOptionValue builtIn="false" value="NO_INIT"/>
 								</option>
 								<option id="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths.798701398" name="Include paths (-I)" superClass="ilg.gnumcueclipse.managedbuild.cross.riscv.option.c.compiler.include.paths" useByScannerDiscovery="true" valueType="includePath">
-									<listOptionValue builtIn="false" value="../bsp/drivers"/>
-									<listOptionValue builtIn="false" value="../bsp/env"/>
-									<listOptionValue builtIn="false" value="../bsp/env/coreplexip-e51-arty"/>
-									<listOptionValue builtIn="false" value="../bsp/include"/>
 									<listOptionValue builtIn="false" value="../../../../bsp/include"/>
 									<listOptionValue builtIn="false" value="../../../../bsp/env"/>
 									<listOptionValue builtIn="false" value="../../../../bsp/env/coreplexip-e51-arty"/>
-- 
cgit v1.2.3


From 29309b4663866d9e6465c4112701265b87aabe16 Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Mon, 22 Jan 2018 23:37:58 -0600
Subject: remove DS_Stores

---
 FreedomStudio/E51FPGA/coreplexip_welcome/.project | 40 -----------------------
 1 file changed, 40 deletions(-)

(limited to 'FreedomStudio/E51FPGA/coreplexip_welcome')

diff --git a/FreedomStudio/E51FPGA/coreplexip_welcome/.project b/FreedomStudio/E51FPGA/coreplexip_welcome/.project
index 55ef108..e2d1392 100644
--- a/FreedomStudio/E51FPGA/coreplexip_welcome/.project
+++ b/FreedomStudio/E51FPGA/coreplexip_welcome/.project
@@ -34,11 +34,6 @@
 			<type>1</type>
 			<locationURI>PARENT-3-PROJECT_LOC/software/coreplexip_welcome/coreplexip_welcome.c</locationURI>
 		</link>
-		<link>
-			<name>bsp/.DS_Store</name>
-			<type>1</type>
-			<locationURI>PARENT-3-PROJECT_LOC/bsp/.DS_Store</locationURI>
-		</link>
 		<link>
 			<name>bsp/drivers</name>
 			<type>2</type>
@@ -59,11 +54,6 @@
 			<type>2</type>
 			<locationURI>virtual:/virtual</locationURI>
 		</link>
-		<link>
-			<name>bsp/drivers/.DS_Store</name>
-			<type>1</type>
-			<locationURI>PARENT-3-PROJECT_LOC/bsp/drivers/.DS_Store</locationURI>
-		</link>
 		<link>
 			<name>bsp/drivers/fe300prci</name>
 			<type>2</type>
@@ -74,11 +64,6 @@
 			<type>2</type>
 			<locationURI>virtual:/virtual</locationURI>
 		</link>
-		<link>
-			<name>bsp/env/.DS_Store</name>
-			<type>1</type>
-			<locationURI>PARENT-3-PROJECT_LOC/bsp/env/.DS_Store</locationURI>
-		</link>
 		<link>
 			<name>bsp/env/coreplexip-arty.h</name>
 			<type>1</type>
@@ -109,21 +94,11 @@
 			<type>1</type>
 			<locationURI>PARENT-3-PROJECT_LOC/bsp/env/start.S</locationURI>
 		</link>
-		<link>
-			<name>bsp/include/.DS_Store</name>
-			<type>1</type>
-			<locationURI>PARENT-3-PROJECT_LOC/bsp/include/.DS_Store</locationURI>
-		</link>
 		<link>
 			<name>bsp/include/sifive</name>
 			<type>2</type>
 			<locationURI>virtual:/virtual</locationURI>
 		</link>
-		<link>
-			<name>bsp/libwrap/.DS_Store</name>
-			<type>1</type>
-			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/.DS_Store</locationURI>
-		</link>
 		<link>
 			<name>bsp/libwrap/misc</name>
 			<type>2</type>
@@ -209,31 +184,16 @@
 			<type>1</type>
 			<locationURI>PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h</locationURI>
 		</link>
-		<link>
-			<name>bsp/libwrap/misc/.DS_Store</name>
-			<type>1</type>
-			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/.DS_Store</locationURI>
-		</link>
 		<link>
 			<name>bsp/libwrap/misc/write_hex.c</name>
 			<type>1</type>
 			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c</locationURI>
 		</link>
-		<link>
-			<name>bsp/libwrap/stdlib/.DS_Store</name>
-			<type>1</type>
-			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/.DS_Store</locationURI>
-		</link>
 		<link>
 			<name>bsp/libwrap/stdlib/malloc.c</name>
 			<type>1</type>
 			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c</locationURI>
 		</link>
-		<link>
-			<name>bsp/libwrap/sys/.DS_Store</name>
-			<type>1</type>
-			<locationURI>PARENT-3-PROJECT_LOC/bsp/libwrap/sys/.DS_Store</locationURI>
-		</link>
 		<link>
 			<name>bsp/libwrap/sys/_exit.c</name>
 			<type>1</type>
-- 
cgit v1.2.3