From 809711e87af06ca5c151a2fac568382330f2feb6 Mon Sep 17 00:00:00 2001
From: Megan Wachs <megan@sifive.com>
Date: Wed, 14 Jun 2017 08:52:57 -0700
Subject: New Freedom Studio Examples (#66)

* examples ported to ilg build plugin

* project cleanup

* CoreplexIP-E31 ilg projects

* E51FPGA ilg projects

* Tested Debug

* debug launch files

* E31 Debug Launch Files

* removed typo project

* E51 launch files. Forgotten E31 File

* Missing coreplexip files

* examples ported to ilg build plugin

* project cleanup

* CoreplexIP-E31 ilg projects

* E51FPGA ilg projects

* Tested Debug

* debug launch files

* E31 Debug Launch Files

* removed typo project

* E51 launch files. Forgotten E31 File

* Missing coreplexip files

* starting fresh

* HiFive1 demo_gpio and libwrap

* hifive1 hello

* debug launchers for hello and demo_gpio

* hifive1 led_fade

* led_fade: Since E300 Arty Dev Kit doesn't have a PRCI, the led_fade demo doesn't really work on it.

* update include paths to ease generating stand-alone zips

* Adding E51 Examples

* E51 demo launch files

* E31 Demos

* E31 demo launch files
---
 .../sifive-coreplexip-e51-arty.cfg                 | 31 ++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 FreedomStudio/E51FPGA/local_interrupts/sifive-coreplexip-e51-arty.cfg

(limited to 'FreedomStudio/E51FPGA/local_interrupts/sifive-coreplexip-e51-arty.cfg')

diff --git a/FreedomStudio/E51FPGA/local_interrupts/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/local_interrupts/sifive-coreplexip-e51-arty.cfg
new file mode 100644
index 0000000..8b382dc
--- /dev/null
+++ b/FreedomStudio/E51FPGA/local_interrupts/sifive-coreplexip-e51-arty.cfg
@@ -0,0 +1,31 @@
+# JTAG adapter setup
+adapter_khz     10000
+
+interface ftdi
+ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi_vid_pid 0x15ba 0x002a
+
+ftdi_layout_init 0x0808 0x0a1b
+ftdi_layout_signal nSRST -oe 0x0200
+#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi_layout_signal LED -data 0x0800
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001
+
+set _TARGETNAME $_CHIPNAME.cpu
+
+target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME
+$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+# Un-comment these two flash lines if you have a SPI flash and want to write
+# it.
+flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000
+init
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+}
+halt
+flash protect 0 64 last off
+echo "Ready for Remote Connections"
-- 
cgit v1.2.1-18-gbd029