From 64115be98dda5eae8840e373c85b0c615f196dbb Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Tue, 25 Jul 2017 16:58:47 -0500 Subject: added vectored interrupt example --- .../E51FPGA/vectored_interrupts/.cproject | 220 +++++++++++++++++++ .../E51FPGA/vectored_interrupts/.gitignore | 1 + FreedomStudio/E51FPGA/vectored_interrupts/.project | 233 +++++++++++++++++++++ .../sifive-coreplexip-e51-arty.cfg | 31 +++ 4 files changed, 485 insertions(+) create mode 100644 FreedomStudio/E51FPGA/vectored_interrupts/.cproject create mode 100644 FreedomStudio/E51FPGA/vectored_interrupts/.gitignore create mode 100644 FreedomStudio/E51FPGA/vectored_interrupts/.project create mode 100644 FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg (limited to 'FreedomStudio/E51FPGA') diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.cproject b/FreedomStudio/E51FPGA/vectored_interrupts/.cproject new file mode 100644 index 0000000..c50fa56 --- /dev/null +++ b/FreedomStudio/E51FPGA/vectored_interrupts/.cproject @@ -0,0 +1,220 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.gitignore b/FreedomStudio/E51FPGA/vectored_interrupts/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/FreedomStudio/E51FPGA/vectored_interrupts/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/.project b/FreedomStudio/E51FPGA/vectored_interrupts/.project new file mode 100644 index 0000000..22e0667 --- /dev/null +++ b/FreedomStudio/E51FPGA/vectored_interrupts/.project @@ -0,0 +1,233 @@ + + + vectored_interrupts + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + bsp + 2 + virtual:/virtual + + + vectored_interrupts.c + 1 + PARENT-3-PROJECT_LOC/software/vectored_interrupts/vectored_interrupts.c + + + bsp/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/.DS_Store + + + bsp/drivers + 2 + virtual:/virtual + + + bsp/env + 2 + virtual:/virtual + + + bsp/include + 2 + virtual:/virtual + + + bsp/drivers/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/.DS_Store + + + bsp/drivers/fe300prci + 2 + virtual:/virtual + + + bsp/drivers/plic + 2 + virtual:/virtual + + + bsp/env/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/env/.DS_Store + + + bsp/env/coreplexip-arty.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h + + + bsp/env/coreplexip-e51-arty + 2 + virtual:/virtual + + + bsp/env/encoding.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/encoding.h + + + bsp/env/hifive1.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/hifive1.h + + + bsp/env/start.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/start.S + + + bsp/env/ventry.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/ventry.S + + + bsp/include/.DS_Store + 1 + PARENT-3-PROJECT_LOC/bsp/include/.DS_Store + + + bsp/include/sifive + 2 + virtual:/virtual + + + bsp/drivers/fe300prci/fe300prci_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c + + + bsp/drivers/fe300prci/fe300prci_driver.h + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.h + + + bsp/drivers/plic/plic_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.c + + + bsp/drivers/plic/plic_driver.h + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/plic/plic_driver.h + + + bsp/env/coreplexip-e51-arty/flash.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/flash.lds + + + bsp/env/coreplexip-e51-arty/init.c + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/init.c + + + bsp/env/coreplexip-e51-arty/openocd.cfg + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/openocd.cfg + + + bsp/env/coreplexip-e51-arty/platform.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/platform.h + + + bsp/env/coreplexip-e51-arty/scratchpad.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-e51-arty/scratchpad.lds + + + bsp/include/sifive/bits.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h + + + bsp/include/sifive/const.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h + + + bsp/include/sifive/devices + 2 + virtual:/virtual + + + bsp/include/sifive/sections.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h + + + bsp/include/sifive/smp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h + + + bsp/include/sifive/devices/aon.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h + + + bsp/include/sifive/devices/clint.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h + + + bsp/include/sifive/devices/gpio.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h + + + bsp/include/sifive/devices/otp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h + + + bsp/include/sifive/devices/plic.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h + + + bsp/include/sifive/devices/prci.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h + + + bsp/include/sifive/devices/pwm.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h + + + bsp/include/sifive/devices/spi.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h + + + bsp/include/sifive/devices/uart.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h + + + diff --git a/FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg b/FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg new file mode 100644 index 0000000..8b382dc --- /dev/null +++ b/FreedomStudio/E51FPGA/vectored_interrupts/sifive-coreplexip-e51-arty.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" -- cgit v1.2.1-18-gbd029