From 6cebe81ad76bd44d71297b5ec19fef0b9a01817f Mon Sep 17 00:00:00 2001 From: Drew Barbier Date: Sun, 8 Jul 2018 18:02:20 -0500 Subject: FS projects --- FreedomStudio/E2FPGA/clic_vectored/.cproject | 208 ++++++++++++ FreedomStudio/E2FPGA/clic_vectored/.gitignore | 1 + FreedomStudio/E2FPGA/clic_vectored/.project | 358 ++++++++++++++++++++ .../E2FPGA/clic_vectored/sifive-coreip-e2-arty.cfg | 31 ++ FreedomStudio/E2FPGA/coreplexip_welcome/.cproject | 210 ++++++++++++ FreedomStudio/E2FPGA/coreplexip_welcome/.gitignore | 1 + FreedomStudio/E2FPGA/coreplexip_welcome/.project | 358 ++++++++++++++++++++ .../coreplexip_welcome/sifive-coreip-e2-arty.cfg | 31 ++ FreedomStudio/E2FPGA/dhrystone/.cproject | 216 ++++++++++++ FreedomStudio/E2FPGA/dhrystone/.gitignore | 1 + FreedomStudio/E2FPGA/dhrystone/.project | 373 +++++++++++++++++++++ .../E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg | 31 ++ 12 files changed, 1819 insertions(+) create mode 100644 FreedomStudio/E2FPGA/clic_vectored/.cproject create mode 100644 FreedomStudio/E2FPGA/clic_vectored/.gitignore create mode 100644 FreedomStudio/E2FPGA/clic_vectored/.project create mode 100644 FreedomStudio/E2FPGA/clic_vectored/sifive-coreip-e2-arty.cfg create mode 100644 FreedomStudio/E2FPGA/coreplexip_welcome/.cproject create mode 100644 FreedomStudio/E2FPGA/coreplexip_welcome/.gitignore create mode 100644 FreedomStudio/E2FPGA/coreplexip_welcome/.project create mode 100644 FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg create mode 100644 FreedomStudio/E2FPGA/dhrystone/.cproject create mode 100644 FreedomStudio/E2FPGA/dhrystone/.gitignore create mode 100644 FreedomStudio/E2FPGA/dhrystone/.project create mode 100644 FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg (limited to 'FreedomStudio') diff --git a/FreedomStudio/E2FPGA/clic_vectored/.cproject b/FreedomStudio/E2FPGA/clic_vectored/.cproject new file mode 100644 index 0000000..85a0e97 --- /dev/null +++ b/FreedomStudio/E2FPGA/clic_vectored/.cproject @@ -0,0 +1,208 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreedomStudio/E2FPGA/clic_vectored/.gitignore b/FreedomStudio/E2FPGA/clic_vectored/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/FreedomStudio/E2FPGA/clic_vectored/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/FreedomStudio/E2FPGA/clic_vectored/.project b/FreedomStudio/E2FPGA/clic_vectored/.project new file mode 100644 index 0000000..171cf91 --- /dev/null +++ b/FreedomStudio/E2FPGA/clic_vectored/.project @@ -0,0 +1,358 @@ + + + clic_vectored + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + bsp + 2 + virtual:/virtual + + + clic_vectored.c + 1 + PARENT-3-PROJECT_LOC/software/clic_vectored/clic_vectored.c + + + bsp/drivers + 2 + virtual:/virtual + + + bsp/env + 2 + virtual:/virtual + + + bsp/include + 2 + virtual:/virtual + + + bsp/libwrap + 2 + virtual:/virtual + + + bsp/drivers/clic + 2 + virtual:/virtual + + + bsp/drivers/fe300prci + 2 + virtual:/virtual + + + bsp/env/coreip-e2-arty + 2 + virtual:/virtual + + + bsp/env/coreplexip-arty.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h + + + bsp/env/encoding.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/encoding.h + + + bsp/env/entry.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/entry.S + + + bsp/env/hifive1.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/hifive1.h + + + bsp/env/start.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/start.S + + + bsp/include/sifive + 2 + virtual:/virtual + + + bsp/libwrap/misc + 2 + virtual:/virtual + + + bsp/libwrap/stdlib + 2 + virtual:/virtual + + + bsp/libwrap/sys + 2 + virtual:/virtual + + + bsp/drivers/clic/clic_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/clic/clic_driver.c + + + bsp/drivers/clic/plic_driver.h + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/clic/clic_driver.h + + + bsp/env/coreip-e2-arty/dhrystone.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/dhrystone.lds + + + bsp/env/coreip-e2-arty/flash.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/flash.lds + + + bsp/env/coreip-e2-arty/init.c + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/init.c + + + bsp/env/coreip-e2-arty/openocd.cfg + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/openocd.cfg + + + bsp/env/coreip-e2-arty/platform.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/platform.h + + + bsp/env/coreip-e2-arty/settings.mk + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/settings.mk + + + bsp/env/coreip-e2-arty/tim-split.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim-split.lds + + + bsp/env/coreip-e2-arty/tim.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim.lds + + + bsp/include/sifive/bits.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h + + + bsp/include/sifive/const.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h + + + bsp/include/sifive/devices + 2 + virtual:/virtual + + + bsp/include/sifive/sections.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h + + + bsp/include/sifive/smp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h + + + bsp/libwrap/misc/write_hex.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c + + + bsp/libwrap/stdlib/malloc.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c + + + bsp/libwrap/sys/_exit.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c + + + bsp/libwrap/sys/close.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c + + + bsp/libwrap/sys/execve.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c + + + bsp/libwrap/sys/fork.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c + + + bsp/libwrap/sys/fstat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c + + + bsp/libwrap/sys/getpid.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c + + + bsp/libwrap/sys/isatty.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c + + + bsp/libwrap/sys/kill.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c + + + bsp/libwrap/sys/link.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c + + + bsp/libwrap/sys/lseek.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c + + + bsp/libwrap/sys/open.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c + + + bsp/libwrap/sys/openat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c + + + bsp/libwrap/sys/puts.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c + + + bsp/libwrap/sys/read.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c + + + bsp/libwrap/sys/sbrk.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c + + + bsp/libwrap/sys/stat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c + + + bsp/libwrap/sys/stub.h + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h + + + bsp/libwrap/sys/times.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c + + + bsp/libwrap/sys/unlink.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c + + + bsp/libwrap/sys/wait.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c + + + bsp/libwrap/sys/weak_under_alias.h + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h + + + bsp/libwrap/sys/write.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c + + + bsp/include/sifive/devices/aon.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h + + + bsp/include/sifive/devices/clint.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h + + + bsp/include/sifive/devices/gpio.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h + + + bsp/include/sifive/devices/otp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h + + + bsp/include/sifive/devices/plic.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h + + + bsp/include/sifive/devices/prci.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h + + + bsp/include/sifive/devices/pwm.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h + + + bsp/include/sifive/devices/spi.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h + + + bsp/include/sifive/devices/uart.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h + + + diff --git a/FreedomStudio/E2FPGA/clic_vectored/sifive-coreip-e2-arty.cfg b/FreedomStudio/E2FPGA/clic_vectored/sifive-coreip-e2-arty.cfg new file mode 100644 index 0000000..8b382dc --- /dev/null +++ b/FreedomStudio/E2FPGA/clic_vectored/sifive-coreip-e2-arty.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/FreedomStudio/E2FPGA/coreplexip_welcome/.cproject b/FreedomStudio/E2FPGA/coreplexip_welcome/.cproject new file mode 100644 index 0000000..051c949 --- /dev/null +++ b/FreedomStudio/E2FPGA/coreplexip_welcome/.cproject @@ -0,0 +1,210 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreedomStudio/E2FPGA/coreplexip_welcome/.gitignore b/FreedomStudio/E2FPGA/coreplexip_welcome/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/FreedomStudio/E2FPGA/coreplexip_welcome/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/FreedomStudio/E2FPGA/coreplexip_welcome/.project b/FreedomStudio/E2FPGA/coreplexip_welcome/.project new file mode 100644 index 0000000..0d91d8d --- /dev/null +++ b/FreedomStudio/E2FPGA/coreplexip_welcome/.project @@ -0,0 +1,358 @@ + + + coreplexip_welcome + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + bsp + 2 + virtual:/virtual + + + coreplexip_welcome.c + 1 + PARENT-3-PROJECT_LOC/software/coreplexip_welcome/coreplexip_welcome.c + + + bsp/drivers + 2 + virtual:/virtual + + + bsp/env + 2 + virtual:/virtual + + + bsp/include + 2 + virtual:/virtual + + + bsp/libwrap + 2 + virtual:/virtual + + + bsp/drivers/clic + 2 + virtual:/virtual + + + bsp/drivers/fe300prci + 2 + virtual:/virtual + + + bsp/env/coreip-e2-arty + 2 + virtual:/virtual + + + bsp/env/coreplexip-arty.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h + + + bsp/env/encoding.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/encoding.h + + + bsp/env/entry.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/entry.S + + + bsp/env/hifive1.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/hifive1.h + + + bsp/env/start.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/start.S + + + bsp/include/sifive + 2 + virtual:/virtual + + + bsp/libwrap/misc + 2 + virtual:/virtual + + + bsp/libwrap/stdlib + 2 + virtual:/virtual + + + bsp/libwrap/sys + 2 + virtual:/virtual + + + bsp/drivers/clic/clic_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/clic/clic_driver.c + + + bsp/drivers/clic/plic_driver.h + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/clic/clic_driver.h + + + bsp/env/coreip-e2-arty/dhrystone.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/dhrystone.lds + + + bsp/env/coreip-e2-arty/flash.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/flash.lds + + + bsp/env/coreip-e2-arty/init.c + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/init.c + + + bsp/env/coreip-e2-arty/openocd.cfg + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/openocd.cfg + + + bsp/env/coreip-e2-arty/platform.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/platform.h + + + bsp/env/coreip-e2-arty/settings.mk + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/settings.mk + + + bsp/env/coreip-e2-arty/tim-split.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim-split.lds + + + bsp/env/coreip-e2-arty/tim.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim.lds + + + bsp/include/sifive/bits.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h + + + bsp/include/sifive/const.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h + + + bsp/include/sifive/devices + 2 + virtual:/virtual + + + bsp/include/sifive/sections.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h + + + bsp/include/sifive/smp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h + + + bsp/libwrap/misc/write_hex.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c + + + bsp/libwrap/stdlib/malloc.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c + + + bsp/libwrap/sys/_exit.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c + + + bsp/libwrap/sys/close.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c + + + bsp/libwrap/sys/execve.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c + + + bsp/libwrap/sys/fork.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c + + + bsp/libwrap/sys/fstat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c + + + bsp/libwrap/sys/getpid.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c + + + bsp/libwrap/sys/isatty.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c + + + bsp/libwrap/sys/kill.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c + + + bsp/libwrap/sys/link.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c + + + bsp/libwrap/sys/lseek.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c + + + bsp/libwrap/sys/open.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c + + + bsp/libwrap/sys/openat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c + + + bsp/libwrap/sys/puts.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c + + + bsp/libwrap/sys/read.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c + + + bsp/libwrap/sys/sbrk.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c + + + bsp/libwrap/sys/stat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c + + + bsp/libwrap/sys/stub.h + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h + + + bsp/libwrap/sys/times.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c + + + bsp/libwrap/sys/unlink.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c + + + bsp/libwrap/sys/wait.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c + + + bsp/libwrap/sys/weak_under_alias.h + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h + + + bsp/libwrap/sys/write.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c + + + bsp/include/sifive/devices/aon.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h + + + bsp/include/sifive/devices/clint.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h + + + bsp/include/sifive/devices/gpio.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h + + + bsp/include/sifive/devices/otp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h + + + bsp/include/sifive/devices/plic.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h + + + bsp/include/sifive/devices/prci.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h + + + bsp/include/sifive/devices/pwm.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h + + + bsp/include/sifive/devices/spi.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h + + + bsp/include/sifive/devices/uart.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h + + + diff --git a/FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg b/FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg new file mode 100644 index 0000000..8b382dc --- /dev/null +++ b/FreedomStudio/E2FPGA/coreplexip_welcome/sifive-coreip-e2-arty.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" diff --git a/FreedomStudio/E2FPGA/dhrystone/.cproject b/FreedomStudio/E2FPGA/dhrystone/.cproject new file mode 100644 index 0000000..863a5a9 --- /dev/null +++ b/FreedomStudio/E2FPGA/dhrystone/.cproject @@ -0,0 +1,216 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + diff --git a/FreedomStudio/E2FPGA/dhrystone/.gitignore b/FreedomStudio/E2FPGA/dhrystone/.gitignore new file mode 100644 index 0000000..3df573f --- /dev/null +++ b/FreedomStudio/E2FPGA/dhrystone/.gitignore @@ -0,0 +1 @@ +/Debug/ diff --git a/FreedomStudio/E2FPGA/dhrystone/.project b/FreedomStudio/E2FPGA/dhrystone/.project new file mode 100644 index 0000000..3407cae --- /dev/null +++ b/FreedomStudio/E2FPGA/dhrystone/.project @@ -0,0 +1,373 @@ + + + dhrystone + + + + + + org.eclipse.cdt.managedbuilder.core.genmakebuilder + clean,full,incremental, + + + + + org.eclipse.cdt.managedbuilder.core.ScannerConfigBuilder + full,incremental, + + + + + + org.eclipse.cdt.core.cnature + org.eclipse.cdt.managedbuilder.core.managedBuildNature + org.eclipse.cdt.managedbuilder.core.ScannerConfigNature + + + + bsp + 2 + virtual:/virtual + + + dhry.h + 1 + PARENT-3-PROJECT_LOC/software/dhrystone/dhry.h + + + dhry_1.c + 1 + PARENT-3-PROJECT_LOC/software/dhrystone/dhry_1.c + + + dhry_2.c + 1 + PARENT-3-PROJECT_LOC/software/dhrystone/dhry_2.c + + + dhry_printf.c + 1 + PARENT-3-PROJECT_LOC/software/dhrystone/dhry_printf.c + + + dhry_stubs.c + 1 + PARENT-3-PROJECT_LOC/software/dhrystone/dhry_stubs.c + + + bsp/drivers + 2 + virtual:/virtual + + + bsp/env + 2 + virtual:/virtual + + + bsp/include + 2 + virtual:/virtual + + + bsp/libwrap + 2 + virtual:/virtual + + + bsp/drivers/fe300prci + 2 + virtual:/virtual + + + bsp/drivers/plic + 2 + virtual:/virtual + + + bsp/env/coreplexip-arty.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreplexip-arty.h + + + bsp/env/coreip-e2-arty + 2 + virtual:/virtual + + + bsp/env/encoding.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/encoding.h + + + bsp/env/entry.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/entry.S + + + bsp/env/hifive1.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/hifive1.h + + + bsp/env/start.S + 1 + PARENT-3-PROJECT_LOC/bsp/env/start.S + + + bsp/include/sifive + 2 + virtual:/virtual + + + bsp/libwrap/misc + 2 + virtual:/virtual + + + bsp/libwrap/stdlib + 2 + virtual:/virtual + + + bsp/libwrap/sys + 2 + virtual:/virtual + + + bsp/drivers/fe300prci/fe300prci_driver.c + 1 + PARENT-3-PROJECT_LOC/bsp/drivers/fe300prci/fe300prci_driver.c + + + bsp/env/coreip-e2-arty/tim-split.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim-split.lds + + + bsp/env/coreip-e2-arty/tim.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/tim.lds + + + bsp/env/coreip-e2-arty/flash.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/flash.lds + + + bsp/env/coreip-e2-arty/init.c + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/init.c + + + bsp/env/coreip-e2-arty/openocd.cfg + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/openocd.cfg + + + bsp/env/coreip-e2-arty/platform.h + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/platform.h + + + bsp/env/coreip-e2-arty/scratchpad.lds + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/scratchpad.lds + + + bsp/env/coreip-e2-arty/settings.mk + 1 + PARENT-3-PROJECT_LOC/bsp/env/coreip-e2-arty/settings.mk + + + bsp/include/sifive/bits.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/bits.h + + + bsp/include/sifive/const.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/const.h + + + bsp/include/sifive/devices + 2 + virtual:/virtual + + + bsp/include/sifive/sections.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/sections.h + + + bsp/include/sifive/smp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/smp.h + + + bsp/libwrap/misc/write_hex.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/misc/write_hex.c + + + bsp/libwrap/stdlib/malloc.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/stdlib/malloc.c + + + bsp/libwrap/sys/_exit.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/_exit.c + + + bsp/libwrap/sys/close.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/close.c + + + bsp/libwrap/sys/execve.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/execve.c + + + bsp/libwrap/sys/fork.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fork.c + + + bsp/libwrap/sys/fstat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/fstat.c + + + bsp/libwrap/sys/getpid.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/getpid.c + + + bsp/libwrap/sys/isatty.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/isatty.c + + + bsp/libwrap/sys/kill.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/kill.c + + + bsp/libwrap/sys/link.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/link.c + + + bsp/libwrap/sys/lseek.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/lseek.c + + + bsp/libwrap/sys/open.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/open.c + + + bsp/libwrap/sys/openat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/openat.c + + + bsp/libwrap/sys/puts.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/puts.c + + + bsp/libwrap/sys/read.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/read.c + + + bsp/libwrap/sys/sbrk.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/sbrk.c + + + bsp/libwrap/sys/stat.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stat.c + + + bsp/libwrap/sys/stub.h + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/stub.h + + + bsp/libwrap/sys/times.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/times.c + + + bsp/libwrap/sys/unlink.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/unlink.c + + + bsp/libwrap/sys/wait.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/wait.c + + + bsp/libwrap/sys/weak_under_alias.h + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/weak_under_alias.h + + + bsp/libwrap/sys/write.c + 1 + PARENT-3-PROJECT_LOC/bsp/libwrap/sys/write.c + + + bsp/include/sifive/devices/aon.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/aon.h + + + bsp/include/sifive/devices/clint.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/clint.h + + + bsp/include/sifive/devices/gpio.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/gpio.h + + + bsp/include/sifive/devices/otp.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/otp.h + + + bsp/include/sifive/devices/plic.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/plic.h + + + bsp/include/sifive/devices/prci.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/prci.h + + + bsp/include/sifive/devices/pwm.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/pwm.h + + + bsp/include/sifive/devices/spi.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/spi.h + + + bsp/include/sifive/devices/uart.h + 1 + PARENT-3-PROJECT_LOC/bsp/include/sifive/devices/uart.h + + + diff --git a/FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg b/FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg new file mode 100644 index 0000000..8b382dc --- /dev/null +++ b/FreedomStudio/E2FPGA/dhrystone/sifive-coreip-e2-arty.cfg @@ -0,0 +1,31 @@ +# JTAG adapter setup +adapter_khz 10000 + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +#ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 -expected-id 0x20000001 + +set _TARGETNAME $_CHIPNAME.cpu + +target create $_TARGETNAME.0 riscv -chain-position $_TARGETNAME +$_TARGETNAME.0 configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +# Un-comment these two flash lines if you have a SPI flash and want to write +# it. +flash bank spi0 fespi 0x40000000 0 0 0 $_TARGETNAME.0 0x20004000 +init +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +flash protect 0 64 last off +echo "Ready for Remote Connections" -- cgit v1.2.3