From e18401806b38ca0f60394780191df4b72cb2f88a Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Mon, 25 Feb 2019 18:57:35 -0800 Subject: Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty --- bsp/coreip-e20/README.md | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 bsp/coreip-e20/README.md (limited to 'bsp/coreip-e20/README.md') diff --git a/bsp/coreip-e20/README.md b/bsp/coreip-e20/README.md new file mode 100644 index 0000000..5e19221 --- /dev/null +++ b/bsp/coreip-e20/README.md @@ -0,0 +1,6 @@ +The SiFive E20 Standard Core is an extremely efficient implementation of the E2 Series configured for very low area and power. The E20 brings the power of the RISC-V software ecosystem to efficiently address traditional 8-bit and 32-bit microcontroller applications such as IoT, Analog Mixed Signal, and Programmable Finite State Machines. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV32IMC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 4 regions -- cgit v1.2.1-18-gbd029