From 15e54fcdc862cedfbc3fc4e8b7c71eae23f93c54 Mon Sep 17 00:00:00 2001
From: Bunnaroath Sou <bsou@sifive.com>
Date: Fri, 22 Feb 2019 17:23:58 -0800
Subject: Adding Standard CoreIPs forE20, E21 support

---
 bsp/coreip-e20/design.dts | 80 +++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 bsp/coreip-e20/design.dts

(limited to 'bsp/coreip-e20/design.dts')

diff --git a/bsp/coreip-e20/design.dts b/bsp/coreip-e20/design.dts
new file mode 100644
index 0000000..f3c25a5
--- /dev/null
+++ b/bsp/coreip-e20/design.dts
@@ -0,0 +1,80 @@
+/dts-v1/;
+
+/ {
+	#address-cells = <1>;
+	#size-cells = <1>;
+	compatible = "SiFive,FE200G-dev", "fe200-dev", "sifive-dev";
+	model = "SiFive,FE200G";
+	L11: cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		L4: cpu@0 {
+			clock-frequency = <0>;
+			compatible = "sifive,caboose0", "riscv";
+			device_type = "cpu";
+			reg = <0x0>;
+			riscv,isa = "rv32imc";
+			status = "okay";
+			timebase-frequency = <1000000>;
+                        hardware-exec-breakpoint-count = <4>;
+			L3: interrupt-controller {
+				#interrupt-cells = <1>;
+				compatible = "riscv,cpu-intc";
+				interrupt-controller;
+			};
+		};
+	};
+	L10: soc {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		compatible = "SiFive,FE200G-soc", "fe200-soc", "sifive-soc", "simple-bus";
+		ranges;
+ 		pmp: pmp@0 {
+ 			compatible = "riscv,pmp";
+ 			regions = <8>;
+ 		};
+		L8: ahb-sys-port@20000000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "sifive,ahb-sys-port", "sifive,ahb-port", "sifive,sys-port", "simple-bus";
+			ranges = <0x20000000 0x20000000 0x20000000>;
+		};
+		L2: debug-controller@0 {
+			compatible = "sifive,debug-013", "riscv,debug-013";
+			interrupts-extended = <&L3 65535>;
+			reg = <0x0 0x1000>;
+			reg-names = "control";
+		};
+		L0: error-device@3000 {
+			compatible = "sifive,error0";
+			reg = <0x3000 0x1000>;
+		};
+		L1: interrupt-controller@2000000 {
+			#interrupt-cells = <1>;
+			compatible = "sifive,clic0";
+			interrupt-controller;
+			interrupts-extended = <&L3 3 &L3 7 &L3 11>;
+			reg = <0x2000000 0x1000000>;
+			reg-names = "control";
+			sifive,numints = <48>;
+			sifive,numlevels = <16>;
+                        sifive,numintbits = <2>;
+		};
+		L7: local-external-interrupts-0 {
+                        compatible = "sifive,local-external-interrupts0";
+			interrupt-parent = <&L1>;
+			interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>;
+		};
+		L5: teststatus@4000 {
+			compatible = "sifive,test0";
+			reg = <0x4000 0x1000>;
+			reg-names = "control";
+		};
+                test_memory: testram@20000000 {
+                        compatible = "sifive,testram0";
+                        reg = <0x20000000 0x8000000>;
+                        reg-names = "mem";
+                        word-size-bytes = <4>;
+                };
+	};
+};
-- 
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