From b87018b8a5afa98a6f799527d9a4417290349a4a Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 21 May 2019 10:51:18 -0700 Subject: Modify BSP DTSs to use riscv,pmpregions property Signed-off-by: Nathaniel Graff --- bsp/coreip-e21-arty/design.dts | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'bsp/coreip-e21-arty') diff --git a/bsp/coreip-e21-arty/design.dts b/bsp/coreip-e21-arty/design.dts index 7303568..40f61d0 100644 --- a/bsp/coreip-e21-arty/design.dts +++ b/bsp/coreip-e21-arty/design.dts @@ -21,6 +21,7 @@ device_type = "cpu"; reg = <0x0>; riscv,isa = "rv32imac"; + riscv,pmpregions = <4>; status = "okay"; timebase-frequency = <32000000>; hardware-exec-breakpoint-count = <4>; @@ -36,10 +37,6 @@ #size-cells = <1>; compatible = "SiFive,FE210G-soc", "fe210-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <4>; - }; hfclk: clock@0 { #clock-cells = <0>; compatible = "fixed-clock"; -- cgit v1.2.3 From c5dd42c68d030a356c85bb8d174296b4f2df615d Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 21 May 2019 10:55:10 -0700 Subject: Update BSPs Signed-off-by: Nathaniel Graff --- bsp/coreip-e21-arty/metal-inline.h | 8 ++------ bsp/coreip-e21-arty/metal-platform.h | 7 +------ bsp/coreip-e21-arty/metal.default.lds | 2 +- bsp/coreip-e21-arty/metal.h | 17 +++++++++++++---- bsp/coreip-e21-arty/metal.ramrodata.lds | 2 +- bsp/coreip-e21-arty/metal.scratchpad.lds | 2 +- bsp/coreip-e21-arty/settings.mk | 2 +- 7 files changed, 20 insertions(+), 20 deletions(-) (limited to 'bsp/coreip-e21-arty') diff --git a/bsp/coreip-e21-arty/metal-inline.h b/bsp/coreip-e21-arty/metal-inline.h index 0f167d5..37937d3 100644 --- a/bsp/coreip-e21-arty/metal-inline.h +++ b/bsp/coreip-e21-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -25,6 +25,7 @@ extern inline unsigned long __metal_driver_fixed_clock_rate(struct metal_clock * /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -173,11 +174,6 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable, diff --git a/bsp/coreip-e21-arty/metal-platform.h b/bsp/coreip-e21-arty/metal-platform.h index 75dc2dd..adbfb15 100644 --- a/bsp/coreip-e21-arty/metal-platform.h +++ b/bsp/coreip-e21-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E21_ARTY__METAL_PLATFORM_H @@ -12,11 +12,6 @@ #define METAL_FIXED_CLOCK -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 4UL - -#define METAL_RISCV_PMP - /* From interrupt_controller@2000000 */ #define METAL_SIFIVE_CLIC0_2000000_BASE_ADDRESS 33554432UL #define METAL_SIFIVE_CLIC0_0_BASE_ADDRESS 33554432UL diff --git a/bsp/coreip-e21-arty/metal.default.lds b/bsp/coreip-e21-arty/metal.default.lds index 0b7a37a..b7665dd 100644 --- a/bsp/coreip-e21-arty/metal.default.lds +++ b/bsp/coreip-e21-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e21-arty/metal.h b/bsp/coreip-e21-arty/metal.h index 89b2931..8ef7fc6 100644 --- a/bsp/coreip-e21-arty/metal.h +++ b/bsp/coreip-e21-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -96,7 +96,7 @@ struct __metal_driver_cpu __metal_dt_cpu_0; struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From interrupt_controller@2000000 */ struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000; @@ -194,6 +194,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 4; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -1226,8 +1236,7 @@ asm (".weak __metal_cpu_table"); struct __metal_driver_cpu *__metal_cpu_table[] = { &__metal_dt_cpu_0}; -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From interrupt_controller@2000000 */ #define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) diff --git a/bsp/coreip-e21-arty/metal.ramrodata.lds b/bsp/coreip-e21-arty/metal.ramrodata.lds index e1e793f..54b0c8e 100644 --- a/bsp/coreip-e21-arty/metal.ramrodata.lds +++ b/bsp/coreip-e21-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e21-arty/metal.scratchpad.lds b/bsp/coreip-e21-arty/metal.scratchpad.lds index e986066..912117d 100644 --- a/bsp/coreip-e21-arty/metal.scratchpad.lds +++ b/bsp/coreip-e21-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e21-arty/settings.mk b/bsp/coreip-e21-arty/settings.mk index b9be584..d7bf600 100644 --- a/bsp/coreip-e21-arty/settings.mk +++ b/bsp/coreip-e21-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imac -- cgit v1.2.3