From f7a18d3711b3bb04b7ed8294a0e47599ac15cf45 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Wed, 6 Mar 2019 11:50:22 -0800 Subject: Update/add E20, E21, E24 arty targets for all 19.2 CoreIPs release --- bsp/coreip-e21-arty/README.md | 14 + bsp/coreip-e21-arty/design.dts | 196 +++++++++++++ bsp/coreip-e21-arty/metal.h | 602 ++++++++++++++++++++++++++++++++++++++++ bsp/coreip-e21-arty/metal.lds | 225 +++++++++++++++ bsp/coreip-e21-arty/openocd.cfg | 30 ++ bsp/coreip-e21-arty/settings.mk | 2 + 6 files changed, 1069 insertions(+) create mode 100644 bsp/coreip-e21-arty/README.md create mode 100644 bsp/coreip-e21-arty/design.dts create mode 100644 bsp/coreip-e21-arty/metal.h create mode 100644 bsp/coreip-e21-arty/metal.lds create mode 100644 bsp/coreip-e21-arty/openocd.cfg create mode 100644 bsp/coreip-e21-arty/settings.mk (limited to 'bsp/coreip-e21-arty') diff --git a/bsp/coreip-e21-arty/README.md b/bsp/coreip-e21-arty/README.md new file mode 100644 index 0000000..e0cb9a7 --- /dev/null +++ b/bsp/coreip-e21-arty/README.md @@ -0,0 +1,14 @@ +The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements. + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Memory Protection with 4 regions +- Up to 153 CLIC interrupt signals that can be connected to off core complex devices, with 16 levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches + diff --git a/bsp/coreip-e21-arty/design.dts b/bsp/coreip-e21-arty/design.dts new file mode 100644 index 0000000..be0c023 --- /dev/null +++ b/bsp/coreip-e21-arty/design.dts @@ -0,0 +1,196 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "SiFive,FE210G-dev", "fe210-dev", "sifive-dev"; + model = "SiFive,FE210G"; + chosen { + stdout-path = "/soc/serial@20000000:115200"; + mee,entry = <&L7 0x400000>; + }; + L17: aliases { + serial0 = &L6; + }; + L16: cpus { + #address-cells = <1>; + #size-cells = <0>; + L4: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,caboose0", "riscv"; + device_type = "cpu"; + reg = <0x0>; + riscv,isa = "rv32imac"; + status = "okay"; + timebase-frequency = <1000000>; + hardware-exec-breakpoint-count = <4>; + L3: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L15: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "SiFive,FE210G-soc", "fe210-soc", "sifive-soc", "simple-bus"; + ranges; + hfclk: clock@0 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32500000>; + }; + L2: debug-controller@0 { + compatible = "sifive,debug-013", "riscv,debug-013"; + interrupts-extended = <&L3 65535>; + reg = <0x0 0x1000>; + reg-names = "control"; + }; + L0: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + }; + L12: global-external-interrupts { + compatible = "sifive,global-external-interrupts0"; + interrupt-parent = <&L1>; + interrupts = <22 23 24 25>; + }; + L5: gpio@20002000 { + #gpio-cells = <2>; + #interrupt-cells = <2>; + compatible = "sifive,gpio0", "sifive,gpio1"; + gpio-controller; + interrupt-controller; + interrupt-parent = <&L1>; + interrupts = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>; + reg = <0x20002000 0x1000>; + reg-names = "control"; + }; + L1: interrupt-controller@2000000 { + #interrupt-cells = <1>; + compatible = "sifive,clic0"; + interrupt-controller; + interrupts-extended = <&L3 3 &L3 7 &L3 11>; + reg = <0x2000000 0x1000000>; + reg-names = "control"; + sifive,numints = <153>; + sifive,numlevels = <16>; + sifive,numintbits = <2>; + }; + L13: local-external-interrupts-0 { + compatible = "sifive,local-external-interrupts0"; + interrupt-parent = <&L1>; + interrupts = <26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152>; + }; + L8: pwm@20005000 { + compatible = "sifive,pwm0"; + interrupt-parent = <&L1>; + interrupts = <18 19 20 21>; + reg = <0x20005000 0x1000>; + reg-names = "control"; + }; + L6: serial@20000000 { + compatible = "sifive,uart0"; + interrupt-parent = <&L1>; + interrupts = <16>; + reg = <0x20000000 0x1000>; + reg-names = "control"; + clocks = <&hfclk>; + }; + L7: spi@20004000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "sifive,spi0"; + interrupt-parent = <&L1>; + interrupts = <17>; + reg = <0x20004000 0x1000 0x40000000 0x20000000>; + reg-names = "control", "mem"; + }; + L10: sys-sram-0@80000000 { + compatible = "sifive,sram0"; + reg = <0x80000000 0x8000>; + reg-names = "mem"; + }; + L11: sys-sram-1@80008000 { + compatible = "sifive,sram0"; + reg = <0x80008000 0x8000>; + reg-names = "mem"; + }; + led@0red { + compatible = "sifive,gpio-leds"; + label = "LD0red"; + gpios = <&L5 0>; + linux,default-trigger = "none"; + }; + led@0green { + compatible = "sifive,gpio-leds"; + label = "LD0green"; + gpios = <&L5 1>; + linux,default-trigger = "none"; + }; + led@0blue { + compatible = "sifive,gpio-leds"; + label = "LD0blue"; + gpios = <&L5 2>; + linux,default-trigger = "none"; + }; + button@0 { + compatible = "sifive,gpio-buttons"; + label = "BTN0"; + gpios = <&L5 4>; + interrupts-extended = <&L13 20>; + linux,code = "none"; + }; + button@1 { + compatible = "sifive,gpio-buttons"; + label = "BTN1"; + gpios = <&L5 5>; + interrupts-extended = <&L13 21>; + linux,code = "none"; + }; + button@2 { + compatible = "sifive,gpio-buttons"; + label = "BTN2"; + gpios = <&L5 6>; + interrupts-extended = <&L13 22>; + linux,code = "none"; + }; + button@3 { + compatible = "sifive,gpio-buttons"; + label = "BTN3"; + gpios = <&L5 7>; + interrupts-extended = <&L13 23>; + linux,code = "none"; + }; + switch@0 { + compatible = "sifive,gpio-switches"; + label = "SW0"; + interrupts-extended = <&L13 16>; + linux,code = "none"; + }; + switch@1 { + compatible = "sifive,gpio-switches"; + label = "SW1"; + interrupts-extended = <&L13 17>; + linux,code = "none"; + }; + switch@2 { + compatible = "sifive,gpio-switches"; + label = "SW2"; + interrupts-extended = <&L13 18>; + linux,code = "none"; + }; + switch@3 { + compatible = "sifive,gpio-switches"; + label = "SW3"; + interrupts-extended = <&L13 19>; + linux,code = "none"; + }; + L9: teststatus@4000 { + compatible = "sifive,test0"; + reg = <0x4000 0x1000>; + reg-names = "control"; + }; + }; +}; diff --git a/bsp/coreip-e21-arty/metal.h b/bsp/coreip-e21-arty/metal.h new file mode 100644 index 0000000..49b4c73 --- /dev/null +++ b/bsp/coreip-e21-arty/metal.h @@ -0,0 +1,602 @@ +#ifndef ASSEMBLY + +#ifndef COREIP_E21_ARTY__METAL_H +#define COREIP_E21_ARTY__METAL_H + +#ifdef __METAL_MACHINE_MACROS + +#define __METAL_CLIC_SUBINTERRUPTS 153 + +#ifndef __METAL_CLIC_SUBINTERRUPTS +#define __METAL_CLIC_SUBINTERRUPTS 0 +#endif + +#else /* ! __METAL_MACHINE_MACROS */ + +#define METAL_MAX_CLINT_INTERRUPTS 0 + +#define METAL_MAX_PLIC_INTERRUPTS 0 + +#define __METAL_INTERRUPT_CONTROLLER_2000000_INTERRUPTS 3 + +#define __METAL_CLIC_SUBINTERRUPTS 153 + +#define METAL_MAX_CLIC_INTERRUPTS 3 + +#define __METAL_LOCAL_EXTERNAL_INTERRUPTS_0_INTERRUPTS 127 + +#define METAL_MAX_LOCAL_EXT_INTERRUPTS 127 + +#define __METAL_GLOBAL_EXTERNAL_INTERRUPTS_INTERRUPTS 4 + +#define METAL_MAX_GLOBAL_EXT_INTERRUPTS 4 + +#define __METAL_GPIO_20002000_INTERRUPTS 16 + +#define METAL_MAX_GPIO_INTERRUPTS 16 + +#define __METAL_SERIAL_20000000_INTERRUPTS 1 + +#define METAL_MAX_UART_INTERRUPTS 1 + + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +/* From clock@0 */ +asm (".weak __metal_dt_clock_0"); +struct __metal_driver_fixed_clock __metal_dt_clock_0; + +/* From cpu@0 */ +asm (".weak __metal_dt_cpu_0"); +struct __metal_driver_cpu __metal_dt_cpu_0; + +/* From interrupt_controller */ +asm (".weak __metal_dt_interrupt_controller"); +struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller; + +/* From interrupt_controller@2000000 */ +asm (".weak __metal_dt_interrupt_controller_2000000"); +struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000; + +/* From local_external_interrupts_0 */ +asm (".weak __metal_dt_local_external_interrupts_0"); +struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0; + +/* From global_external_interrupts */ +asm (".weak __metal_dt_global_external_interrupts"); +struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; + +/* From gpio@20002000 */ +asm (".weak __metal_dt_gpio_20002000"); +struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000; + +/* From button@0 */ +asm (".weak __metal_dt_button_0"); +struct __metal_driver_sifive_gpio_button __metal_dt_button_0; + +/* From button@1 */ +asm (".weak __metal_dt_button_1"); +struct __metal_driver_sifive_gpio_button __metal_dt_button_1; + +/* From button@2 */ +asm (".weak __metal_dt_button_2"); +struct __metal_driver_sifive_gpio_button __metal_dt_button_2; + +/* From button@3 */ +asm (".weak __metal_dt_button_3"); +struct __metal_driver_sifive_gpio_button __metal_dt_button_3; + +/* From led@0red */ +asm (".weak __metal_dt_led_0red"); +struct __metal_driver_sifive_gpio_led __metal_dt_led_0red; + +/* From led@0green */ +asm (".weak __metal_dt_led_0green"); +struct __metal_driver_sifive_gpio_led __metal_dt_led_0green; + +/* From led@0blue */ +asm (".weak __metal_dt_led_0blue"); +struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue; + +/* From switch@0 */ +asm (".weak __metal_dt_switch_0"); +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0; + +/* From switch@1 */ +asm (".weak __metal_dt_switch_1"); +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1; + +/* From switch@2 */ +asm (".weak __metal_dt_switch_2"); +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2; + +/* From switch@3 */ +asm (".weak __metal_dt_switch_3"); +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3; + +/* From spi@20004000 */ +asm (".weak __metal_dt_spi_20004000"); +struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000; + +/* From teststatus@4000 */ +asm (".weak __metal_dt_teststatus_4000"); +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000; + +/* From serial@20000000 */ +asm (".weak __metal_dt_serial_20000000"); +struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000; + + +/* From clock@0 */ +struct __metal_driver_fixed_clock __metal_dt_clock_0 = { + .vtable = &__metal_driver_vtable_fixed_clock, + .clock.vtable = &__metal_driver_vtable_fixed_clock.clock, + .rate = 32500000UL, +}; + +/* From cpu@0 */ +struct __metal_driver_cpu __metal_dt_cpu_0 = { + .vtable = &__metal_driver_vtable_cpu, + .cpu.vtable = &__metal_driver_vtable_cpu.cpu_vtable, + .timebase = 1000000UL, + .interrupt_controller = &__metal_dt_interrupt_controller.controller, +}; + +/* From interrupt_controller */ +struct __metal_driver_riscv_cpu_intc __metal_dt_interrupt_controller = { + .vtable = &__metal_driver_vtable_riscv_cpu_intc, + .controller.vtable = &__metal_driver_vtable_riscv_cpu_intc.controller_vtable, + .init_done = 0, + .interrupt_controller = 1, +}; + +/* From interrupt_controller@2000000 */ +struct __metal_driver_sifive_clic0 __metal_dt_interrupt_controller_2000000 = { + .vtable = &__metal_driver_vtable_sifive_clic0, + .controller.vtable = &__metal_driver_vtable_sifive_clic0.clic_vtable, + .control_base = 33554432UL, + .control_size = 16777216UL, + .init_done = 0, + .num_interrupts = METAL_MAX_CLIC_INTERRUPTS, + .interrupt_parent = &__metal_dt_interrupt_controller.controller, + .interrupt_lines[0] = 3, + .interrupt_lines[1] = 7, + .interrupt_lines[2] = 11, + .num_subinterrupts = 153UL, + .num_intbits = 2UL, + .max_levels = 16UL, + .interrupt_controller = 1, +}; + +/* From local_external_interrupts_0 */ +struct __metal_driver_sifive_local_external_interrupts0 __metal_dt_local_external_interrupts_0 = { + .vtable = &__metal_driver_vtable_sifive_local_external_interrupts0, + .irc.vtable = &__metal_driver_vtable_sifive_local_external_interrupts0.local0_vtable, + .init_done = 0, +/* From interrupt_controller@2000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller, + .num_interrupts = METAL_MAX_LOCAL_EXT_INTERRUPTS, + .interrupt_lines[0] = 26, + .interrupt_lines[1] = 27, + .interrupt_lines[2] = 28, + .interrupt_lines[3] = 29, + .interrupt_lines[4] = 30, + .interrupt_lines[5] = 31, + .interrupt_lines[6] = 32, + .interrupt_lines[7] = 33, + .interrupt_lines[8] = 34, + .interrupt_lines[9] = 35, + .interrupt_lines[10] = 36, + .interrupt_lines[11] = 37, + .interrupt_lines[12] = 38, + .interrupt_lines[13] = 39, + .interrupt_lines[14] = 40, + .interrupt_lines[15] = 41, + .interrupt_lines[16] = 42, + .interrupt_lines[17] = 43, + .interrupt_lines[18] = 44, + .interrupt_lines[19] = 45, + .interrupt_lines[20] = 46, + .interrupt_lines[21] = 47, + .interrupt_lines[22] = 48, + .interrupt_lines[23] = 49, + .interrupt_lines[24] = 50, + .interrupt_lines[25] = 51, + .interrupt_lines[26] = 52, + .interrupt_lines[27] = 53, + .interrupt_lines[28] = 54, + .interrupt_lines[29] = 55, + .interrupt_lines[30] = 56, + .interrupt_lines[31] = 57, + .interrupt_lines[32] = 58, + .interrupt_lines[33] = 59, + .interrupt_lines[34] = 60, + .interrupt_lines[35] = 61, + .interrupt_lines[36] = 62, + .interrupt_lines[37] = 63, + .interrupt_lines[38] = 64, + .interrupt_lines[39] = 65, + .interrupt_lines[40] = 66, + .interrupt_lines[41] = 67, + .interrupt_lines[42] = 68, + .interrupt_lines[43] = 69, + .interrupt_lines[44] = 70, + .interrupt_lines[45] = 71, + .interrupt_lines[46] = 72, + .interrupt_lines[47] = 73, + .interrupt_lines[48] = 74, + .interrupt_lines[49] = 75, + .interrupt_lines[50] = 76, + .interrupt_lines[51] = 77, + .interrupt_lines[52] = 78, + .interrupt_lines[53] = 79, + .interrupt_lines[54] = 80, + .interrupt_lines[55] = 81, + .interrupt_lines[56] = 82, + .interrupt_lines[57] = 83, + .interrupt_lines[58] = 84, + .interrupt_lines[59] = 85, + .interrupt_lines[60] = 86, + .interrupt_lines[61] = 87, + .interrupt_lines[62] = 88, + .interrupt_lines[63] = 89, + .interrupt_lines[64] = 90, + .interrupt_lines[65] = 91, + .interrupt_lines[66] = 92, + .interrupt_lines[67] = 93, + .interrupt_lines[68] = 94, + .interrupt_lines[69] = 95, + .interrupt_lines[70] = 96, + .interrupt_lines[71] = 97, + .interrupt_lines[72] = 98, + .interrupt_lines[73] = 99, + .interrupt_lines[74] = 100, + .interrupt_lines[75] = 101, + .interrupt_lines[76] = 102, + .interrupt_lines[77] = 103, + .interrupt_lines[78] = 104, + .interrupt_lines[79] = 105, + .interrupt_lines[80] = 106, + .interrupt_lines[81] = 107, + .interrupt_lines[82] = 108, + .interrupt_lines[83] = 109, + .interrupt_lines[84] = 110, + .interrupt_lines[85] = 111, + .interrupt_lines[86] = 112, + .interrupt_lines[87] = 113, + .interrupt_lines[88] = 114, + .interrupt_lines[89] = 115, + .interrupt_lines[90] = 116, + .interrupt_lines[91] = 117, + .interrupt_lines[92] = 118, + .interrupt_lines[93] = 119, + .interrupt_lines[94] = 120, + .interrupt_lines[95] = 121, + .interrupt_lines[96] = 122, + .interrupt_lines[97] = 123, + .interrupt_lines[98] = 124, + .interrupt_lines[99] = 125, + .interrupt_lines[100] = 126, + .interrupt_lines[101] = 127, + .interrupt_lines[102] = 128, + .interrupt_lines[103] = 129, + .interrupt_lines[104] = 130, + .interrupt_lines[105] = 131, + .interrupt_lines[106] = 132, + .interrupt_lines[107] = 133, + .interrupt_lines[108] = 134, + .interrupt_lines[109] = 135, + .interrupt_lines[110] = 136, + .interrupt_lines[111] = 137, + .interrupt_lines[112] = 138, + .interrupt_lines[113] = 139, + .interrupt_lines[114] = 140, + .interrupt_lines[115] = 141, + .interrupt_lines[116] = 142, + .interrupt_lines[117] = 143, + .interrupt_lines[118] = 144, + .interrupt_lines[119] = 145, + .interrupt_lines[120] = 146, + .interrupt_lines[121] = 147, + .interrupt_lines[122] = 148, + .interrupt_lines[123] = 149, + .interrupt_lines[124] = 150, + .interrupt_lines[125] = 151, + .interrupt_lines[126] = 152, +}; + +/* From global_external_interrupts */ +struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { + .vtable = &__metal_driver_vtable_sifive_global_external_interrupts0, + .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, + .init_done = 0, +/* From interrupt_controller@2000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller, + .num_interrupts = METAL_MAX_GLOBAL_EXT_INTERRUPTS, + .interrupt_lines[0] = 22, + .interrupt_lines[1] = 23, + .interrupt_lines[2] = 24, + .interrupt_lines[3] = 25, +}; + +/* From gpio@20002000 */ +struct __metal_driver_sifive_gpio0 __metal_dt_gpio_20002000 = { + .vtable = &__metal_driver_vtable_sifive_gpio0, + .base = 536879104UL, + .size = 4096UL, +/* From interrupt_controller@2000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller, + .num_interrupts = METAL_MAX_GPIO_INTERRUPTS, + .interrupt_lines[0] = 0, + .interrupt_lines[1] = 1, + .interrupt_lines[2] = 2, + .interrupt_lines[3] = 3, + .interrupt_lines[4] = 4, + .interrupt_lines[5] = 5, + .interrupt_lines[6] = 6, + .interrupt_lines[7] = 7, + .interrupt_lines[8] = 8, + .interrupt_lines[9] = 9, + .interrupt_lines[10] = 10, + .interrupt_lines[11] = 11, + .interrupt_lines[12] = 12, + .interrupt_lines[13] = 13, + .interrupt_lines[14] = 14, + .interrupt_lines[15] = 15, +}; + +/* From button@0 */ +struct __metal_driver_sifive_gpio_button __metal_dt_button_0 = { + .vtable = &__metal_driver_vtable_sifive_button, + .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 4UL, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 20UL, + .label = "BTN0", +}; + +/* From button@1 */ +struct __metal_driver_sifive_gpio_button __metal_dt_button_1 = { + .vtable = &__metal_driver_vtable_sifive_button, + .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 5UL, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 21UL, + .label = "BTN1", +}; + +/* From button@2 */ +struct __metal_driver_sifive_gpio_button __metal_dt_button_2 = { + .vtable = &__metal_driver_vtable_sifive_button, + .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 6UL, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 22UL, + .label = "BTN2", +}; + +/* From button@3 */ +struct __metal_driver_sifive_gpio_button __metal_dt_button_3 = { + .vtable = &__metal_driver_vtable_sifive_button, + .button.vtable = &__metal_driver_vtable_sifive_button.button_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 7UL, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 23UL, + .label = "BTN3", +}; + +/* From led@0red */ +struct __metal_driver_sifive_gpio_led __metal_dt_led_0red = { + .vtable = &__metal_driver_vtable_sifive_led, + .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 0UL, + .label = "LD0red", +}; + +/* From led@0green */ +struct __metal_driver_sifive_gpio_led __metal_dt_led_0green = { + .vtable = &__metal_driver_vtable_sifive_led, + .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 1UL, + .label = "LD0green", +}; + +/* From led@0blue */ +struct __metal_driver_sifive_gpio_led __metal_dt_led_0blue = { + .vtable = &__metal_driver_vtable_sifive_led, + .led.vtable = &__metal_driver_vtable_sifive_led.led_vtable, +/* From gpio@20002000 */ + .gpio = &__metal_dt_gpio_20002000, + .pin = 2UL, + .label = "LD0blue", +}; + +/* From switch@0 */ +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_0 = { + .vtable = &__metal_driver_vtable_sifive_switch, + .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable, + .gpio = NULL, + .pin = 0, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 16UL, + .label = "SW0", +}; + +/* From switch@1 */ +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_1 = { + .vtable = &__metal_driver_vtable_sifive_switch, + .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable, + .gpio = NULL, + .pin = 0, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 17UL, + .label = "SW1", +}; + +/* From switch@2 */ +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_2 = { + .vtable = &__metal_driver_vtable_sifive_switch, + .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable, + .gpio = NULL, + .pin = 0, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 18UL, + .label = "SW2", +}; + +/* From switch@3 */ +struct __metal_driver_sifive_gpio_switch __metal_dt_switch_3 = { + .vtable = &__metal_driver_vtable_sifive_switch, + .flip.vtable = &__metal_driver_vtable_sifive_switch.switch_vtable, + .gpio = NULL, + .pin = 0, +/* From local_external_interrupts_0 */ + .interrupt_parent = &__metal_dt_local_external_interrupts_0.irc, + .interrupt_line = 19UL, + .label = "SW3", +}; + +/* From spi@20004000 */ +struct __metal_driver_sifive_spi0 __metal_dt_spi_20004000 = { + .vtable = &__metal_driver_vtable_sifive_spi0, + .spi.vtable = &__metal_driver_vtable_sifive_spi0.spi, + .control_base = 536887296UL, + .control_size = 4096UL, + .clock = NULL, + .pinmux = NULL, +}; + +/* From teststatus@4000 */ +struct __metal_driver_sifive_test0 __metal_dt_teststatus_4000 = { + .vtable = &__metal_driver_vtable_sifive_test0, + .shutdown.vtable = &__metal_driver_vtable_sifive_test0.shutdown, + .base = 16384UL, + .size = 4096UL, +}; + +/* From serial@20000000 */ +struct __metal_driver_sifive_uart0 __metal_dt_serial_20000000 = { + .vtable = &__metal_driver_vtable_sifive_uart0, + .uart.vtable = &__metal_driver_vtable_sifive_uart0.uart, + .control_base = 536870912UL, + .control_size = 4096UL, +/* From clock@0 */ + .clock = &__metal_dt_clock_0.clock, + .pinmux = NULL, +/* From interrupt_controller@2000000 */ + .interrupt_parent = &__metal_dt_interrupt_controller_2000000.controller, + .num_interrupts = METAL_MAX_UART_INTERRUPTS, + .interrupt_line = 16UL, +}; + + +/* From serial@20000000 */ +#define __METAL_DT_STDOUT_UART_HANDLE (&__metal_dt_serial_20000000.uart) + +#define __METAL_DT_SERIAL_20000000_HANDLE (&__metal_dt_serial_20000000.uart) + +#define __METAL_DT_STDOUT_UART_BAUD 115200 + +/* From cpu@0 */ +#define __METAL_DT_RISCV_CPU_HANDLE (&__metal_dt_cpu_0.cpu) + +#define __METAL_DT_CPU_0_HANDLE (&__metal_dt_cpu_0.cpu) + +#define __METAL_DT_MAX_HARTS 1 + +asm (".weak __metal_cpu_table"); +struct __metal_driver_cpu *__metal_cpu_table[] = { + &__metal_dt_cpu_0}; + +/* From interrupt_controller */ +#define __METAL_DT_RISCV_CPU_INTC_HANDLE (&__metal_dt_interrupt_controller.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_HANDLE (&__metal_dt_interrupt_controller.controller) + +/* From interrupt_controller@2000000 */ +#define __METAL_DT_SIFIVE_CLIC0_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) + +#define __METAL_DT_INTERRUPT_CONTROLLER_2000000_HANDLE (&__metal_dt_interrupt_controller_2000000.controller) + +/* From local_external_interrupts_0 */ +#define __METAL_DT_SIFIVE_LOCAL_EXINTR0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) + +#define __METAL_DT_LOCAL_EXTERNAL_INTERRUPTS_0_HANDLE (&__metal_dt_local_external_interrupts_0.irc) + +/* From global_external_interrupts */ +#define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) + +#define __METAL_DT_GLOBAL_EXTERNAL_INTERRUPTS_HANDLE (&__metal_dt_global_external_interrupts.irc) + +#define __METAL_DT_MAX_BUTTONS 4 + +asm (".weak __metal_button_table"); +struct __metal_driver_sifive_gpio_button *__metal_button_table[] = { + &__metal_dt_button_0, + &__metal_dt_button_1, + &__metal_dt_button_2, + &__metal_dt_button_3}; + +#define __METAL_DT_MAX_LEDS 3 + +asm (".weak __metal_led_table"); +struct __metal_driver_sifive_gpio_led *__metal_led_table[] = { + &__metal_dt_led_0red, + &__metal_dt_led_0green, + &__metal_dt_led_0blue}; + +#define __METAL_DT_MAX_SWITCHES 4 + +asm (".weak __metal_switch_table"); +struct __metal_driver_sifive_gpio_switch *__metal_switch_table[] = { + &__metal_dt_switch_0, + &__metal_dt_switch_1, + &__metal_dt_switch_2, + &__metal_dt_switch_3}; + +#define __METAL_DT_MAX_SPIS 1 + +asm (".weak __metal_spi_table"); +struct __metal_driver_sifive_spi0 *__metal_spi_table[] = { + &__metal_dt_spi_20004000}; + +/* From teststatus@4000 */ +#define __METAL_DT_SHUTDOWN_HANDLE (&__metal_dt_teststatus_4000.shutdown) + +#define __METAL_DT_TESTSTATUS_4000_HANDLE (&__metal_dt_teststatus_4000.shutdown) + + +#endif /* ! __METAL_MACHINE_MACROS */ +#endif /* COREIP_E21_ARTY__METAL_H*/ +#endif /* ! ASSEMBLY */ diff --git a/bsp/coreip-e21-arty/metal.lds b/bsp/coreip-e21-arty/metal.lds new file mode 100644 index 0000000..ea41b72 --- /dev/null +++ b/bsp/coreip-e21-arty/metal.lds @@ -0,0 +1,225 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 0x10000 + flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 0x20000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + itim_init PT_LOAD; + ram PT_NULL; + itim PT_NULL; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + + + .init : + { + KEEP (*(.text.metal.init.enter)) + KEEP (*(SORT_NONE(.init))) + } >flash AT>flash :flash + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.itim .itim.*) + *(.gnu.linkonce.t.*) + } >flash AT>flash :flash + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >flash AT>flash :flash + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >flash AT>flash :flash + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >flash AT>flash :flash + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >flash AT>flash :flash + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >flash AT>flash :flash + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >flash AT>flash :flash + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >flash AT>flash :flash + + + .litimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_source_start = . ); + } >flash AT>flash :flash + + + .ditimalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_itim_target_start = . ); + } >ram AT>flash :ram_init + + + .itim : + { + } >flash AT>flash :flash + + + . = ALIGN(8); + PROVIDE( metal_segment_itim_target_end = . ); + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( metal_segment_data_source_start = . ); + } >flash AT>flash :flash + + + .dalign : + { + . = ALIGN(4); + PROVIDE( metal_segment_data_target_start = . ); + } >ram AT>flash :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>flash :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( metal_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( metal_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( metal_segment_bss_target_end = . ); + + + .stack : + { + PROVIDE(metal_segment_stack_begin = .); + . = __stack_size; + PROVIDE( _sp = . ); + PROVIDE(metal_segment_stack_end = .); + } >ram AT>ram :ram + + + .heap : + { + PROVIDE( metal_segment_heap_target_start = . ); + . = __heap_size; + . = __heap_size == 0 ? 0 : ORIGIN(ram) + LENGTH(ram); + PROVIDE( metal_segment_heap_target_end = . ); + PROVIDE( _heap_end = . ); + } >ram AT>ram :ram + + +} + diff --git a/bsp/coreip-e21-arty/openocd.cfg b/bsp/coreip-e21-arty/openocd.cfg new file mode 100644 index 0000000..34b9f88 --- /dev/null +++ b/bsp/coreip-e21-arty/openocd.cfg @@ -0,0 +1,30 @@ +adapter_khz 10000 + +#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg] + +interface ftdi +ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H" +ftdi_vid_pid 0x15ba 0x002a + +ftdi_layout_init 0x0808 0x0a1b +ftdi_layout_signal nSRST -oe 0x0200 +ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100 +ftdi_layout_signal LED -data 0x0800 +# + +set _CHIPNAME riscv +jtag newtap $_CHIPNAME cpu -irlen 5 + +set _TARGETNAME $_CHIPNAME.cpu +target create $_TARGETNAME riscv -chain-position $_TARGETNAME +$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1 + +flash bank my_first_flash fespi 0x40000000 0 0 0 $_TARGETNAME 0x20004000 +init +#reset +if {[ info exists pulse_srst]} { + ftdi_set_signal nSRST 0 + ftdi_set_signal nSRST z +} +halt +#flash protect 0 64 last off diff --git a/bsp/coreip-e21-arty/settings.mk b/bsp/coreip-e21-arty/settings.mk new file mode 100644 index 0000000..31143b5 --- /dev/null +++ b/bsp/coreip-e21-arty/settings.mk @@ -0,0 +1,2 @@ +RISCV_ARCH=rv32imac +RISCV_ABI=ilp32 -- cgit v1.2.3