From e18401806b38ca0f60394780191df4b72cb2f88a Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Mon, 25 Feb 2019 18:57:35 -0800 Subject: Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty --- bsp/coreip-e21/README.md | 6 ++++++ 1 file changed, 6 insertions(+) create mode 100644 bsp/coreip-e21/README.md (limited to 'bsp/coreip-e21') diff --git a/bsp/coreip-e21/README.md b/bsp/coreip-e21/README.md new file mode 100644 index 0000000..31719b3 --- /dev/null +++ b/bsp/coreip-e21/README.md @@ -0,0 +1,6 @@ +The SiFive E21 Standard Core is a high-performance, full-featured embedded processor designed to address advanced microcontroller applications such as Sensor Fusion, Smart IoT, Wearables, Connected Toys, and more. Separate Instruction and Data Buses, along with 2 banks of Tightly Integrated Memory (TIMs) make the E21 an ideal choice for applications with deterministic or demanding memory requirements. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV32IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 4 regions -- cgit v1.2.3