From b87018b8a5afa98a6f799527d9a4417290349a4a Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 21 May 2019 10:51:18 -0700 Subject: Modify BSP DTSs to use riscv,pmpregions property Signed-off-by: Nathaniel Graff --- bsp/coreip-e24-arty/design.dts | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'bsp/coreip-e24-arty') diff --git a/bsp/coreip-e24-arty/design.dts b/bsp/coreip-e24-arty/design.dts index f288b54..ba6b037 100644 --- a/bsp/coreip-e24-arty/design.dts +++ b/bsp/coreip-e24-arty/design.dts @@ -21,6 +21,7 @@ device_type = "cpu"; reg = <0x0>; riscv,isa = "rv32imafc"; + riscv,pmpregions = <4>; status = "okay"; timebase-frequency = <32000000>; hardware-exec-breakpoint-count = <4>; @@ -36,10 +37,6 @@ #size-cells = <1>; compatible = "SiFive,FE240G-soc", "fe240-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <4>; - }; hfclk: clock@0 { #clock-cells = <0>; compatible = "fixed-clock"; -- cgit v1.2.3