From 04654e6c468e853ddef3423221bbda1c8e999dd6 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Tue, 5 Mar 2019 15:29:37 -0800 Subject: Update/add E31, E34, S51, S54 arty targets for all 19.2 CoreIPs release --- bsp/coreip-e24-arty/README.md | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 bsp/coreip-e24-arty/README.md (limited to 'bsp/coreip-e24-arty') diff --git a/bsp/coreip-e24-arty/README.md b/bsp/coreip-e24-arty/README.md new file mode 100644 index 0000000..79dfae8 --- /dev/null +++ b/bsp/coreip-e24-arty/README.md @@ -0,0 +1,13 @@ +The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capabilities by implementing the RISC-V ISA’s F standard extension. The E24’s efficiency, coupled with hardware floating-point capabilities, make it exceptional at motor control, sensor fusion, and IoT applications. + +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAFC core +- 4 hardware breakpoints +- Physical Memory Protection with 4 regions +- Up to 153 CLIC interrupt signals that can be connected to off core complex devices, with 16 levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 interrupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches -- cgit v1.2.3