From 983a630b07f08af869adc78cb37bf634389519af Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Thu, 7 Mar 2019 11:28:06 -0800 Subject: Rename coreip-X to coreip-X-rtl Signed-off-by: Nathaniel Graff --- bsp/coreip-e24-rtl/README.md | 8 ++++++++ 1 file changed, 8 insertions(+) create mode 100644 bsp/coreip-e24-rtl/README.md (limited to 'bsp/coreip-e24-rtl/README.md') diff --git a/bsp/coreip-e24-rtl/README.md b/bsp/coreip-e24-rtl/README.md new file mode 100644 index 0000000..1996262 --- /dev/null +++ b/bsp/coreip-e24-rtl/README.md @@ -0,0 +1,8 @@ +The SiFive E24 Standard Core is a high-performance microcontroller with hardware support for single-precision floating-point capabilities by implementing the RISC-V ISA’s F standard extension. The E24’s efficiency, coupled with hardware floating-point capabilities, make it exceptional at motor control, sensor fusion, and IoT applications. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV32IMAFC core +- 4 hardware breakpoints +- Physical Memory Protection with 4 regions + -- cgit v1.2.1-18-gbd029