From 0d6aad1a8c3b806716add4b5bb6954984d508ab3 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Wed, 19 Jun 2019 15:26:20 -0700 Subject: Delete coreip BSPs Signed-off-by: Nathaniel Graff --- bsp/coreip-e31-arty/README.md | 14 -------------- 1 file changed, 14 deletions(-) delete mode 100644 bsp/coreip-e31-arty/README.md (limited to 'bsp/coreip-e31-arty/README.md') diff --git a/bsp/coreip-e31-arty/README.md b/bsp/coreip-e31-arty/README.md deleted file mode 100644 index c6558cb..0000000 --- a/bsp/coreip-e31-arty/README.md +++ /dev/null @@ -1,14 +0,0 @@ -The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. - -This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: - -- 1 hart with RV32IMAC core -- 4 hardware breakpoints -- Physical Memory Protection with 8 regions -- 16 local interrupts signal that can be connected to off core complex devices -- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels -- GPIO memory with 16 interrupt lines -- SPI memory with 1 interrupt line -- Serial port with 1 interrupt line -- 4 RGB LEDS -- 4 Buttons and 4 Switches -- cgit v1.2.1-18-gbd029