From 6f093407b960b296cf578fa446a4dd82aa674236 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Thu, 13 Dec 2018 14:04:04 -0800 Subject: Add MEE BSP for E31 CoreIP Signed-off-by: Nathaniel Graff --- bsp/coreip-e31/design.dts | 105 +++++++++++++++++++++++++ bsp/coreip-e31/mee.h | 17 ++++ bsp/coreip-e31/mee.lds | 189 +++++++++++++++++++++++++++++++++++++++++++++ bsp/coreip-e31/settings.mk | 4 + 4 files changed, 315 insertions(+) create mode 100644 bsp/coreip-e31/design.dts create mode 100644 bsp/coreip-e31/mee.h create mode 100644 bsp/coreip-e31/mee.lds create mode 100644 bsp/coreip-e31/settings.mk (limited to 'bsp/coreip-e31') diff --git a/bsp/coreip-e31/design.dts b/bsp/coreip-e31/design.dts new file mode 100644 index 0000000..3884085 --- /dev/null +++ b/bsp/coreip-e31/design.dts @@ -0,0 +1,105 @@ +/dts-v1/; + +/ { + #address-cells = <1>; + #size-cells = <1>; + compatible = "SiFive,FE310G-dev", "fe310-dev", "sifive-dev"; + model = "SiFive,FE310G"; + L15: cpus { + #address-cells = <1>; + #size-cells = <0>; + L6: cpu@0 { + clock-frequency = <0>; + compatible = "sifive,rocket0", "riscv"; + device_type = "cpu"; + i-cache-block-size = <64>; + i-cache-sets = <128>; + i-cache-size = <16384>; + reg = <0>; + riscv,isa = "rv32imac"; + sifive,dtim = <&L5>; + sifive,itim = <&L4>; + status = "okay"; + timebase-frequency = <1000000>; + L3: interrupt-controller { + #interrupt-cells = <1>; + compatible = "riscv,cpu-intc"; + interrupt-controller; + }; + }; + }; + L14: soc { + #address-cells = <1>; + #size-cells = <1>; + compatible = "SiFive,FE310G-soc", "fe310-soc", "sifive-soc", "simple-bus"; + ranges; + L12: ahb-periph-port@20000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x20000000 0x20000000 0x20000000>; + }; + L11: ahb-sys-port@40000000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "simple-bus"; + ranges = <0x40000000 0x40000000 0x20000000>; + }; + L1: clint@2000000 { + compatible = "riscv,clint0"; + interrupts-extended = <&L3 3 &L3 7>; + reg = <0x2000000 0x10000>; + reg-names = "control"; + }; + L2: debug-controller@0 { + compatible = "sifive,debug-013", "riscv,debug-013"; + interrupts-extended = <&L3 65535>; + reg = <0x0 0x1000>; + reg-names = "control"; + }; + L5: dtim@80000000 { + compatible = "sifive,dtim0"; + reg = <0x80000000 0x10000>; + reg-names = "mem"; + }; + L8: error-device@3000 { + compatible = "sifive,error0"; + reg = <0x3000 0x1000>; + reg-names = "mem"; + }; + L9: global-external-interrupts { + interrupt-parent = <&L0>; + interrupts = <1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127>; + }; + L0: interrupt-controller@c000000 { + #interrupt-cells = <1>; + compatible = "riscv,plic0"; + interrupt-controller; + interrupts-extended = <&L3 11>; + reg = <0xc000000 0x4000000>; + reg-names = "control"; + riscv,max-priority = <7>; + riscv,ndev = <127>; + }; + L4: itim@8000000 { + compatible = "sifive,itim0"; + reg = <0x8000000 0x4000>; + reg-names = "mem"; + }; + L10: local-external-interrupts-0 { + interrupt-parent = <&L3>; + interrupts = <16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31>; + }; + L7: teststatus@4000 { + compatible = "sifive,test0"; + reg = <0x4000 0x1000>; + reg-names = "control"; + }; + test_memory: testram@20000000 { + compatible = "sifive,testram0"; + reg = <0x20000000 0x8000000>; + reg-names = "mem"; + word-size-bytes = <4>; + }; + }; +}; diff --git a/bsp/coreip-e31/mee.h b/bsp/coreip-e31/mee.h new file mode 100644 index 0000000..39520a3 --- /dev/null +++ b/bsp/coreip-e31/mee.h @@ -0,0 +1,17 @@ +#ifndef ASSEMBLY +#include +/* From teststatus@4000 */ +asm (".weak __mee_dt_teststatus_4000"); +struct __mee_driver_sifive_test0 __mee_dt_teststatus_4000; + +/* From teststatus@4000 */ +struct __mee_driver_sifive_test0 __mee_dt_teststatus_4000 = { + .vtable = &__mee_driver_vtable_sifive_test0, + .shutdown.vtable = &__mee_driver_vtable_sifive_test0.shutdown, + .base = 16384UL, + .size = 4096UL, +}; + +/* From teststatus@4000 */ +#define __MEE_DT_SHUTDOWN_HANDLE (&__mee_dt_teststatus_4000.shutdown) +#endif/*ASSEMBLY*/ diff --git a/bsp/coreip-e31/mee.lds b/bsp/coreip-e31/mee.lds new file mode 100644 index 0000000..c446555 --- /dev/null +++ b/bsp/coreip-e31/mee.lds @@ -0,0 +1,189 @@ +OUTPUT_ARCH("riscv") + +ENTRY(_enter) + +MEMORY +{ + ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 0x8000000 +} + +PHDRS +{ + flash PT_LOAD; + ram_init PT_LOAD; + ram PT_LOAD; +} + +SECTIONS +{ + __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; + + + .init : + { + KEEP (*(.text.mee.init.enter)) + KEEP (*(SORT_NONE(.init))) + } >ram AT>ram :ram + + + .text : + { + *(.text.unlikely .text.unlikely.*) + *(.text.startup .text.startup.*) + *(.text .text.*) + *(.gnu.linkonce.t.*) + } >ram AT>ram :ram + + + .fini : + { + KEEP (*(SORT_NONE(.fini))) + } >ram AT>ram :ram + + + PROVIDE (__etext = .); + PROVIDE (_etext = .); + PROVIDE (etext = .); + + + .rodata : + { + *(.rdata) + *(.rodata .rodata.*) + *(.gnu.linkonce.r.*) + } >ram AT>ram :ram + + + . = ALIGN(4); + + + .preinit_array : + { + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP (*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + } >ram AT>ram :ram + + + .init_array : + { + PROVIDE_HIDDEN (__init_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*))) + KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors)) + PROVIDE_HIDDEN (__init_array_end = .); + } >ram AT>ram :ram + + + .finit_array : + { + PROVIDE_HIDDEN (__finit_array_start = .); + KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*))) + KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors)) + PROVIDE_HIDDEN (__finit_array_end = .); + } >ram AT>ram :ram + + + .ctors : + { + /* gcc uses crtbegin.o to find the start of + the constructors, so we make sure it is + first. Because this is a wildcard, it + doesn't matter if the user does not + actually link against crtbegin.o; the + linker won't look for a file to match a + wildcard. The wildcard also means that it + doesn't matter which directory crtbegin.o + is in. */ + KEEP (*crtbegin.o(.ctors)) + KEEP (*crtbegin?.o(.ctors)) + /* We don't want to include the .ctor section from + the crtend.o file until after the sorted ctors. + The .ctor section from the crtend file contains the + end of ctors marker and it must be last */ + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors)) + KEEP (*(SORT(.ctors.*))) + KEEP (*(.ctors)) + } >ram AT>ram :ram + + + .dtors : + { + KEEP (*crtbegin.o(.dtors)) + KEEP (*crtbegin?.o(.dtors)) + KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors)) + KEEP (*(SORT(.dtors.*))) + KEEP (*(.dtors)) + } >ram AT>ram :ram + + + .lalign : + { + . = ALIGN(4); + PROVIDE( _data_lma = . ); + PROVIDE( mee_segment_data_source_start = . ); + } >ram AT>ram :ram + + + .dalign : + { + . = ALIGN(4); + PROVIDE( mee_segment_data_target_start = . ); + } >ram AT>ram :ram_init + + + .data : + { + *(.data .data.*) + *(.gnu.linkonce.d.*) + . = ALIGN(8); + PROVIDE( __global_pointer$ = . + 0x800 ); + *(.sdata .sdata.*) + *(.gnu.linkonce.s.*) + . = ALIGN(8); + *(.srodata.cst16) + *(.srodata.cst8) + *(.srodata.cst4) + *(.srodata.cst2) + *(.srodata .srodata.*) + } >ram AT>ram :ram_init + + + . = ALIGN(4); + PROVIDE( _edata = . ); + PROVIDE( edata = . ); + PROVIDE( mee_segment_data_target_end = . ); + PROVIDE( _fbss = . ); + PROVIDE( __bss_start = . ); + PROVIDE( mee_segment_bss_target_start = . ); + + + .bss : + { + *(.sbss*) + *(.gnu.linkonce.sb.*) + *(.bss .bss.*) + *(.gnu.linkonce.b.*) + *(COMMON) + . = ALIGN(4); + } >ram AT>ram :ram + + + . = ALIGN(8); + PROVIDE( _end = . ); + PROVIDE( end = . ); + PROVIDE( mee_segment_bss_target_end = . ); + PROVIDE( mee_segment_heap_target_start = . ); + + + .stack : + { + . = ALIGN(8); + . += __stack_size; + PROVIDE( _sp = . ); + PROVIDE( _heap_end = . ); + PROVIDE(mee_segment_stack_end = .); + } >ram AT>ram :ram + + +} + diff --git a/bsp/coreip-e31/settings.mk b/bsp/coreip-e31/settings.mk new file mode 100644 index 0000000..eacecc3 --- /dev/null +++ b/bsp/coreip-e31/settings.mk @@ -0,0 +1,4 @@ +#write_config_file + +RISCV_ARCH=rv32imac +RISCV_ABI=ilp32 -- cgit v1.2.1-18-gbd029