From e18401806b38ca0f60394780191df4b72cb2f88a Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Mon, 25 Feb 2019 18:57:35 -0800 Subject: Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty --- bsp/coreip-e31/README.md | 9 +++++++++ 1 file changed, 9 insertions(+) create mode 100644 bsp/coreip-e31/README.md (limited to 'bsp/coreip-e31') diff --git a/bsp/coreip-e31/README.md b/bsp/coreip-e31/README.md new file mode 100644 index 0000000..02f7723 --- /dev/null +++ b/bsp/coreip-e31/README.md @@ -0,0 +1,9 @@ +The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV32IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 8 regions + - 16 local interrupts signal that can be connected to off core complex devices + - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +~ -- cgit v1.2.3 From 2ee3eec227ca11e0355358aa553b4618fff50bd9 Mon Sep 17 00:00:00 2001 From: Kevin Mills Date: Tue, 26 Feb 2019 08:02:01 -0800 Subject: Add corrected formatting for bullet lists Markdown bullet lists should: (1) have a blank line before and after the list; (2) start each list item at the beginning of the line (no leading white-space) The markdown processor in Freedom Studio enforces these standards and does not render correctly otherwise. --- bsp/coreip-e31/README.md | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) (limited to 'bsp/coreip-e31') diff --git a/bsp/coreip-e31/README.md b/bsp/coreip-e31/README.md index 02f7723..ebfe371 100644 --- a/bsp/coreip-e31/README.md +++ b/bsp/coreip-e31/README.md @@ -1,9 +1,9 @@ The SiFive E31 Standard Core is the world’s most deployed RISC-V core. Co-designed alongside the RISC-V ISA, the E31 takes maximum advantage of the RISC-V ISA, resulting in a power-efficient core that delivers the high performance needed for tomorrow’s smart IoT, storage, and industrial applications. This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV32IMAC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 8 regions - - 16 local interrupts signal that can be connected to off core complex devices - - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels -~ + +- 1 hart with RV32IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels -- cgit v1.2.3 From cbda1f5070e04de7ed3770d5dfd2e4f9abfc84b0 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Wed, 27 Feb 2019 15:46:57 -0800 Subject: Spellcheck correction readme for bsp targets for E20, E21, E31/Arty, S51/Arty --- bsp/coreip-e31/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'bsp/coreip-e31') diff --git a/bsp/coreip-e31/README.md b/bsp/coreip-e31/README.md index ebfe371..324369d 100644 --- a/bsp/coreip-e31/README.md +++ b/bsp/coreip-e31/README.md @@ -4,6 +4,6 @@ This core target is suitable with Verilog RTL for verification and running appli - 1 hart with RV32IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels -- cgit v1.2.3