From 0fe5ca97956cc15effd0c459a81c8caacbc80ac3 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Mon, 18 Mar 2019 12:58:11 -0700 Subject: Update Arty clock to reflects HW --- bsp/coreip-e34-arty/design.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'bsp/coreip-e34-arty/design.dts') diff --git a/bsp/coreip-e34-arty/design.dts b/bsp/coreip-e34-arty/design.dts index 55f3d23..d0e640b 100644 --- a/bsp/coreip-e34-arty/design.dts +++ b/bsp/coreip-e34-arty/design.dts @@ -28,7 +28,7 @@ sifive,dtim = <&L6>; sifive,itim = <&L5>; status = "okay"; - timebase-frequency = <1000000>; + timebase-frequency = <65000000>; hardware-exec-breakpoint-count = <4>; L4: interrupt-controller { #interrupt-cells = <1>; -- cgit v1.2.1-18-gbd029