From 04654e6c468e853ddef3423221bbda1c8e999dd6 Mon Sep 17 00:00:00 2001
From: Bunnaroath Sou <bsou@sifive.com>
Date: Tue, 5 Mar 2019 15:29:37 -0800
Subject: Update/add E31, E34, S51, S54 arty targets for all 19.2 CoreIPs
 release

---
 bsp/coreip-e34-arty/openocd.cfg | 30 ++++++++++++++++++++++++++++++
 1 file changed, 30 insertions(+)
 create mode 100644 bsp/coreip-e34-arty/openocd.cfg

(limited to 'bsp/coreip-e34-arty/openocd.cfg')

diff --git a/bsp/coreip-e34-arty/openocd.cfg b/bsp/coreip-e34-arty/openocd.cfg
new file mode 100644
index 0000000..34b9f88
--- /dev/null
+++ b/bsp/coreip-e34-arty/openocd.cfg
@@ -0,0 +1,30 @@
+adapter_khz     10000
+
+#source [find interface/ftdi/olimex-arm-usb-tiny-h.cfg]
+
+interface ftdi
+ftdi_device_desc "Olimex OpenOCD JTAG ARM-USB-TINY-H"
+ftdi_vid_pid 0x15ba 0x002a
+
+ftdi_layout_init 0x0808 0x0a1b
+ftdi_layout_signal nSRST -oe 0x0200
+ftdi_layout_signal nTRST -data 0x0100 -oe 0x0100
+ftdi_layout_signal LED -data 0x0800
+#
+
+set _CHIPNAME riscv
+jtag newtap $_CHIPNAME cpu -irlen 5
+
+set _TARGETNAME $_CHIPNAME.cpu
+target create $_TARGETNAME riscv -chain-position $_TARGETNAME
+$_TARGETNAME configure -work-area-phys 0x80000000 -work-area-size 10000 -work-area-backup 1
+
+flash bank my_first_flash fespi 0x40000000 0 0 0 $_TARGETNAME 0x20004000
+init
+#reset
+if {[ info exists pulse_srst]} {
+  ftdi_set_signal nSRST 0
+  ftdi_set_signal nSRST z
+}
+halt
+#flash protect 0 64 last off
-- 
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