From 12485f45ebb7f96dc60951bf4365533652ac5139 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Thu, 23 May 2019 14:16:04 -0700 Subject: Update BSPs Signed-off-by: Nathaniel Graff --- bsp/coreip-e76-arty/metal-inline.h | 2 +- bsp/coreip-e76-arty/metal-platform.h | 2 +- bsp/coreip-e76-arty/metal.default.lds | 3 ++- bsp/coreip-e76-arty/metal.h | 24 ++++++++++++------------ bsp/coreip-e76-arty/metal.ramrodata.lds | 3 ++- bsp/coreip-e76-arty/metal.scratchpad.lds | 3 ++- bsp/coreip-e76-arty/settings.mk | 4 +++- 7 files changed, 23 insertions(+), 18 deletions(-) (limited to 'bsp/coreip-e76-arty') diff --git a/bsp/coreip-e76-arty/metal-inline.h b/bsp/coreip-e76-arty/metal-inline.h index d1af334..d1ec2ff 100644 --- a/bsp/coreip-e76-arty/metal-inline.h +++ b/bsp/coreip-e76-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-01 */ /* ----------------------------------- */ #ifndef ASSEMBLY diff --git a/bsp/coreip-e76-arty/metal-platform.h b/bsp/coreip-e76-arty/metal-platform.h index a08971f..237a951 100644 --- a/bsp/coreip-e76-arty/metal-platform.h +++ b/bsp/coreip-e76-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-01 */ /* ----------------------------------- */ #ifndef COREIP_E76_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-e76-arty/metal.default.lds b/bsp/coreip-e76-arty/metal.default.lds index fc983a7..573538c 100644 --- a/bsp/coreip-e76-arty/metal.default.lds +++ b/bsp/coreip-e76-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-01 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-e76-arty/metal.h b/bsp/coreip-e76-arty/metal.h index 0c4f0eb..51cf900 100644 --- a/bsp/coreip-e76-arty/metal.h +++ b/bsp/coreip-e76-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-01 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -75,18 +75,18 @@ #include #include -#include -#include -#include +#include +#include +#include #include -#include -#include -#include -#include -#include -#include -#include -#include +#include +#include +#include +#include +#include +#include +#include +#include /* From tlclk */ struct __metal_driver_fixed_clock __metal_dt_tlclk; diff --git a/bsp/coreip-e76-arty/metal.ramrodata.lds b/bsp/coreip-e76-arty/metal.ramrodata.lds index f53fd33..e44853a 100644 --- a/bsp/coreip-e76-arty/metal.ramrodata.lds +++ b/bsp/coreip-e76-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-01 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-e76-arty/metal.scratchpad.lds b/bsp/coreip-e76-arty/metal.scratchpad.lds index eadc43f..f467347 100644 --- a/bsp/coreip-e76-arty/metal.scratchpad.lds +++ b/bsp/coreip-e76-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 23-05-2019 13-29-49 */ +/* [XXXXX] 28-05-2019 10-06-01 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -29,6 +29,7 @@ SECTIONS PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; PROVIDE(__metal_boot_hart = 0); + PROVIDE(__metal_chicken_bit = 1); .init : diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk index 1e501a6..87b6174 100644 --- a/bsp/coreip-e76-arty/settings.mk +++ b/bsp/coreip-e76-arty/settings.mk @@ -1,12 +1,14 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 23-05-2019 13-29-49 # +# [XXXXX] 28-05-2019 10-06-01 # # ----------------------------------- # RISCV_ARCH=rv32imafc RISCV_ABI=ilp32f RISCV_CMODEL=medlow +RISCV_SERIES=sifive-7-series TARGET_TAGS=fpga openocd TARGET_DHRY_ITERS=20000000 +TARGET_CORE_ITERS=5000 -- cgit v1.2.3