From b87018b8a5afa98a6f799527d9a4417290349a4a Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 21 May 2019 10:51:18 -0700 Subject: Modify BSP DTSs to use riscv,pmpregions property Signed-off-by: Nathaniel Graff --- bsp/coreip-e76-arty/design.dts | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-) (limited to 'bsp/coreip-e76-arty') diff --git a/bsp/coreip-e76-arty/design.dts b/bsp/coreip-e76-arty/design.dts index 1ea526f..c1ef3b2 100644 --- a/bsp/coreip-e76-arty/design.dts +++ b/bsp/coreip-e76-arty/design.dts @@ -28,6 +28,7 @@ next-level-cache = <&L14 &L15>; reg = <0x0>; riscv,isa = "rv32imafc"; + riscv,pmpregions = <8>; status = "okay"; timebase-frequency = <65000000>; hardware-exec-breakpoint-count = <4>; @@ -47,10 +48,6 @@ #size-cells = <1>; compatible = "SiFive,FE710G-soc", "fe710-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L2: clint@2000000 { compatible = "riscv,clint0"; interrupts-extended = <&L4 3 &L4 7>; -- cgit v1.2.3 From c5dd42c68d030a356c85bb8d174296b4f2df615d Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 21 May 2019 10:55:10 -0700 Subject: Update BSPs Signed-off-by: Nathaniel Graff --- bsp/coreip-e76-arty/metal-inline.h | 8 ++------ bsp/coreip-e76-arty/metal-platform.h | 7 +------ bsp/coreip-e76-arty/metal.default.lds | 2 +- bsp/coreip-e76-arty/metal.h | 17 +++++++++++++---- bsp/coreip-e76-arty/metal.ramrodata.lds | 2 +- bsp/coreip-e76-arty/metal.scratchpad.lds | 2 +- bsp/coreip-e76-arty/settings.mk | 2 +- 7 files changed, 20 insertions(+), 20 deletions(-) (limited to 'bsp/coreip-e76-arty') diff --git a/bsp/coreip-e76-arty/metal-inline.h b/bsp/coreip-e76-arty/metal-inline.h index bd8e58b..79d9511 100644 --- a/bsp/coreip-e76-arty/metal-inline.h +++ b/bsp/coreip-e76-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -30,6 +30,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -174,11 +175,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-e76-arty/metal-platform.h b/bsp/coreip-e76-arty/metal-platform.h index d99248d..229fecc 100644 --- a/bsp/coreip-e76-arty/metal-platform.h +++ b/bsp/coreip-e76-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef COREIP_E76_ARTY__METAL_PLATFORM_H @@ -40,11 +40,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From global_external_interrupts */ #define METAL_SIFIVE_GLOBAL_EXTERNAL_INTERRUPTS0 diff --git a/bsp/coreip-e76-arty/metal.default.lds b/bsp/coreip-e76-arty/metal.default.lds index 5f18721..b9fd8c7 100644 --- a/bsp/coreip-e76-arty/metal.default.lds +++ b/bsp/coreip-e76-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e76-arty/metal.h b/bsp/coreip-e76-arty/metal.h index 21a9416..a48daa4 100644 --- a/bsp/coreip-e76-arty/metal.h +++ b/bsp/coreip-e76-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -106,7 +106,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_0_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -257,6 +257,16 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -891,8 +901,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-e76-arty/metal.ramrodata.lds b/bsp/coreip-e76-arty/metal.ramrodata.lds index 2399c34..5a48635 100644 --- a/bsp/coreip-e76-arty/metal.ramrodata.lds +++ b/bsp/coreip-e76-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e76-arty/metal.scratchpad.lds b/bsp/coreip-e76-arty/metal.scratchpad.lds index f218377..5abe56e 100644 --- a/bsp/coreip-e76-arty/metal.scratchpad.lds +++ b/bsp/coreip-e76-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-10 */ +/* [XXXXX] 21-05-2019 10-54-34 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk index 115db75..429208f 100644 --- a/bsp/coreip-e76-arty/settings.mk +++ b/bsp/coreip-e76-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-10 # +# [XXXXX] 21-05-2019 10-54-34 # # ----------------------------------- # RISCV_ARCH=rv32imafc -- cgit v1.2.3 From 2cc2f5e07ad2bfdefc03d443a533d1c5455c283f Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Wed, 22 May 2019 13:39:43 -0700 Subject: Update BSPs Signed-off-by: Nathaniel Graff --- bsp/coreip-e76-arty/metal-inline.h | 3 ++- bsp/coreip-e76-arty/metal-platform.h | 2 +- bsp/coreip-e76-arty/metal.default.lds | 3 ++- bsp/coreip-e76-arty/metal.h | 12 +++++++++++- bsp/coreip-e76-arty/metal.ramrodata.lds | 3 ++- bsp/coreip-e76-arty/metal.scratchpad.lds | 3 ++- bsp/coreip-e76-arty/settings.mk | 3 ++- 7 files changed, 22 insertions(+), 7 deletions(-) (limited to 'bsp/coreip-e76-arty') diff --git a/bsp/coreip-e76-arty/metal-inline.h b/bsp/coreip-e76-arty/metal-inline.h index 79d9511..d1af334 100644 --- a/bsp/coreip-e76-arty/metal-inline.h +++ b/bsp/coreip-e76-arty/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 21-05-2019 10-54-34 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -28,6 +28,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); diff --git a/bsp/coreip-e76-arty/metal-platform.h b/bsp/coreip-e76-arty/metal-platform.h index 229fecc..a08971f 100644 --- a/bsp/coreip-e76-arty/metal-platform.h +++ b/bsp/coreip-e76-arty/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 21-05-2019 10-54-34 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_E76_ARTY__METAL_PLATFORM_H diff --git a/bsp/coreip-e76-arty/metal.default.lds b/bsp/coreip-e76-arty/metal.default.lds index b9fd8c7..fc983a7 100644 --- a/bsp/coreip-e76-arty/metal.default.lds +++ b/bsp/coreip-e76-arty/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 21-05-2019 10-54-34 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e76-arty/metal.h b/bsp/coreip-e76-arty/metal.h index a48daa4..0c4f0eb 100644 --- a/bsp/coreip-e76-arty/metal.h +++ b/bsp/coreip-e76-arty/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 21-05-2019 10-54-34 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -237,6 +237,16 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { diff --git a/bsp/coreip-e76-arty/metal.ramrodata.lds b/bsp/coreip-e76-arty/metal.ramrodata.lds index 5a48635..f53fd33 100644 --- a/bsp/coreip-e76-arty/metal.ramrodata.lds +++ b/bsp/coreip-e76-arty/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 21-05-2019 10-54-34 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e76-arty/metal.scratchpad.lds b/bsp/coreip-e76-arty/metal.scratchpad.lds index 5abe56e..eadc43f 100644 --- a/bsp/coreip-e76-arty/metal.scratchpad.lds +++ b/bsp/coreip-e76-arty/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 21-05-2019 10-54-34 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 0); .init : diff --git a/bsp/coreip-e76-arty/settings.mk b/bsp/coreip-e76-arty/settings.mk index 429208f..1e501a6 100644 --- a/bsp/coreip-e76-arty/settings.mk +++ b/bsp/coreip-e76-arty/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 21-05-2019 10-54-34 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv32imafc @@ -9,3 +9,4 @@ RISCV_ABI=ilp32f RISCV_CMODEL=medlow TARGET_TAGS=fpga openocd +TARGET_DHRY_ITERS=20000000 -- cgit v1.2.3