From e18401806b38ca0f60394780191df4b72cb2f88a Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Mon, 25 Feb 2019 18:57:35 -0800 Subject: Adding readme to bsp targets for E20, E21, E31/Arty, S51/Arty --- bsp/coreip-s51-arty/README.md | 13 +++++++++++++ 1 file changed, 13 insertions(+) create mode 100644 bsp/coreip-s51-arty/README.md (limited to 'bsp/coreip-s51-arty') diff --git a/bsp/coreip-s51-arty/README.md b/bsp/coreip-s51-arty/README.md new file mode 100644 index 0000000..6d6c04f --- /dev/null +++ b/bsp/coreip-s51-arty/README.md @@ -0,0 +1,13 @@ +The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications + +This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: + - 1 hart with RV64IMAC core + - 4 hardware breakpoints + - Physical Mempory Protectin with 8 regions + - 16 local interrupts signal that can be connected to off core complex devices + - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels + - GPIO memory with 16 interrupt lines + - SPI memory with 1 intterupt line + - Serial port with 1 interrupt line + - 4 RGB LEDS + - 4 Buttons and 4 Switches -- cgit v1.2.3 From 2ee3eec227ca11e0355358aa553b4618fff50bd9 Mon Sep 17 00:00:00 2001 From: Kevin Mills Date: Tue, 26 Feb 2019 08:02:01 -0800 Subject: Add corrected formatting for bullet lists Markdown bullet lists should: (1) have a blank line before and after the list; (2) start each list item at the beginning of the line (no leading white-space) The markdown processor in Freedom Studio enforces these standards and does not render correctly otherwise. --- bsp/coreip-s51-arty/README.md | 21 +++++++++++---------- 1 file changed, 11 insertions(+), 10 deletions(-) (limited to 'bsp/coreip-s51-arty') diff --git a/bsp/coreip-s51-arty/README.md b/bsp/coreip-s51-arty/README.md index 6d6c04f..be9d317 100644 --- a/bsp/coreip-s51-arty/README.md +++ b/bsp/coreip-s51-arty/README.md @@ -1,13 +1,14 @@ The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: - - 1 hart with RV64IMAC core - - 4 hardware breakpoints - - Physical Mempory Protectin with 8 regions - - 16 local interrupts signal that can be connected to off core complex devices - - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - - GPIO memory with 16 interrupt lines - - SPI memory with 1 intterupt line - - Serial port with 1 interrupt line - - 4 RGB LEDS - - 4 Buttons and 4 Switches + +- 1 hart with RV64IMAC core +- 4 hardware breakpoints +- Physical Mempory Protectin with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- GPIO memory with 16 interrupt lines +- SPI memory with 1 intterupt line +- Serial port with 1 interrupt line +- 4 RGB LEDS +- 4 Buttons and 4 Switches -- cgit v1.2.3 From cbda1f5070e04de7ed3770d5dfd2e4f9abfc84b0 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Wed, 27 Feb 2019 15:46:57 -0800 Subject: Spellcheck correction readme for bsp targets for E20, E21, E31/Arty, S51/Arty --- bsp/coreip-s51-arty/README.md | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) (limited to 'bsp/coreip-s51-arty') diff --git a/bsp/coreip-s51-arty/README.md b/bsp/coreip-s51-arty/README.md index be9d317..0290171 100644 --- a/bsp/coreip-s51-arty/README.md +++ b/bsp/coreip-s51-arty/README.md @@ -1,14 +1,14 @@ The SiFive S51 Standard Core is a 64-bit embedded processor, fully compliant with the RISC-V ISA. A small-footprint, low-power design makes the S51 ideal for devices that require a tiny system controller in a larger 64-bit SoC. The S51 can also be used as a standalone controller for networking, storage, or other high-performance embedded applications -This FPGA core target is ideal maker and hobbist to develop running application software building on top of freedom-metal libraries. The target supports: +This FPGA core target is ideal for makers and hobbyists to develop running application software building on top of freedom-metal libraries. The target supports: - 1 hart with RV64IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels - GPIO memory with 16 interrupt lines -- SPI memory with 1 intterupt line +- SPI memory with 1 interrupt line - Serial port with 1 interrupt line - 4 RGB LEDS - 4 Buttons and 4 Switches -- cgit v1.2.3