From b87018b8a5afa98a6f799527d9a4417290349a4a Mon Sep 17 00:00:00 2001
From: Nathaniel Graff <nathaniel.graff@sifive.com>
Date: Tue, 21 May 2019 10:51:18 -0700
Subject: Modify BSP DTSs to use riscv,pmpregions property

Signed-off-by: Nathaniel Graff <nathaniel.graff@sifive.com>
---
 bsp/coreip-s51-rtl/design.dts | 5 +----
 1 file changed, 1 insertion(+), 4 deletions(-)

(limited to 'bsp/coreip-s51-rtl')

diff --git a/bsp/coreip-s51-rtl/design.dts b/bsp/coreip-s51-rtl/design.dts
index bbbab4d..3a7bf54 100644
--- a/bsp/coreip-s51-rtl/design.dts
+++ b/bsp/coreip-s51-rtl/design.dts
@@ -17,6 +17,7 @@
 			i-cache-size = <16384>;
 			reg = <0x0>;
 			riscv,isa = "rv64imac";
+			riscv,pmpregions = <8>;
 			sifive,dtim = <&L6>;
 			sifive,itim = <&L5>;
 			status = "okay";
@@ -34,10 +35,6 @@
 		#size-cells = <2>;
 		compatible = "SiFive,FS510G-soc", "fs510-soc", "sifive-soc", "simple-bus";
 		ranges;
-		pmp: pmp@0 {
-			compatible = "riscv,pmp";
-			regions = <8>;
-		};
 		L12: axi4-periph-port@20000000 {
 			#address-cells = <2>;
 			#size-cells = <2>;
-- 
cgit v1.2.1-18-gbd029