From c8611b1e729931796c0403023c755b694439853a Mon Sep 17 00:00:00 2001
From: Nathaniel Graff <nathaniel.graff@sifive.com>
Date: Tue, 18 Dec 2018 13:15:24 -0800
Subject: Update BSPs for ITIM
---
bsp/coreip-s51/mee.lds | 27 +++++++++++++++++++++++++++
1 file changed, 27 insertions(+)
(limited to 'bsp/coreip-s51')
diff --git a/bsp/coreip-s51/mee.lds b/bsp/coreip-s51/mee.lds
index 9f73234..3e454a7 100644
--- a/bsp/coreip-s51/mee.lds
+++ b/bsp/coreip-s51/mee.lds
@@ -4,6 +4,7 @@ ENTRY(_enter)
MEMORY
{
+ itim (wx!rai) : ORIGIN = 0x8000000, LENGTH = 0x4000
ram (wxa!ri) : ORIGIN = 0x20000000, LENGTH = 0x4000000
}
@@ -11,7 +12,9 @@ PHDRS
{
flash PT_LOAD;
ram_init PT_LOAD;
+ itim_init PT_LOAD;
ram PT_LOAD;
+ itim PT_LOAD;
}
SECTIONS
@@ -116,6 +119,30 @@ SECTIONS
} >ram AT>ram :ram
+ .litimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_source_start = . );
+ } >ram AT>ram :ram
+
+
+ .ditimalign :
+ {
+ . = ALIGN(4);
+ PROVIDE( mee_segment_itim_target_start = . );
+ } >itim AT>ram :itim_init
+
+
+ .itim :
+ {
+ *(.itim .itim.*)
+ } >itim AT>ram :itim_init
+
+
+ . = ALIGN(8);
+ PROVIDE( mee_segment_itim_target_end = . );
+
+
.lalign :
{
. = ALIGN(4);
--
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