From cbda1f5070e04de7ed3770d5dfd2e4f9abfc84b0 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Wed, 27 Feb 2019 15:46:57 -0800 Subject: Spellcheck correction readme for bsp targets for E20, E21, E31/Arty, S51/Arty --- bsp/coreip-s51/README.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) (limited to 'bsp/coreip-s51') diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md index a640a47..60f75bf 100644 --- a/bsp/coreip-s51/README.md +++ b/bsp/coreip-s51/README.md @@ -4,6 +4,6 @@ This core target is suitable with Verilog RTL for verification and running appli - 1 hart with RV64IMAC core - 4 hardware breakpoints -- Physical Mempory Protectin with 8 regions +- Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices - Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels -- cgit v1.2.3