From e7a3c3a2999a7b1ffbab96b5bc83061ca6f387d3 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Fri, 1 Mar 2019 19:09:27 -0800 Subject: Add CoreIPs E76, S76 for 19.2 rel --- bsp/coreip-s51/README.md | 2 +- bsp/coreip-s51/settings.mk | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) (limited to 'bsp/coreip-s51') diff --git a/bsp/coreip-s51/README.md b/bsp/coreip-s51/README.md index 60f75bf..bf808d1 100644 --- a/bsp/coreip-s51/README.md +++ b/bsp/coreip-s51/README.md @@ -6,4 +6,4 @@ This core target is suitable with Verilog RTL for verification and running appli - 4 hardware breakpoints - Physical Memory Protection with 8 regions - 16 local interrupts signal that can be connected to off core complex devices -- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels diff --git a/bsp/coreip-s51/settings.mk b/bsp/coreip-s51/settings.mk index 002e8cd..553417e 100644 --- a/bsp/coreip-s51/settings.mk +++ b/bsp/coreip-s51/settings.mk @@ -1,3 +1,3 @@ RISCV_ARCH=rv64imac RISCV_ABI=lp64 -COREIP_MEM_WIDTH=32 +COREIP_MEM_WIDTH=64 -- cgit v1.2.3