From d546fffdae400e6bf86e5f0304f412ff2ca6a641 Mon Sep 17 00:00:00 2001 From: Bunnaroath Sou Date: Fri, 1 Mar 2019 16:04:13 -0800 Subject: Add CoreIPs E34, S54 and update S51 for 19.2 rel --- bsp/coreip-s54/README.md | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 bsp/coreip-s54/README.md (limited to 'bsp/coreip-s54/README.md') diff --git a/bsp/coreip-s54/README.md b/bsp/coreip-s54/README.md new file mode 100644 index 0000000..07b7159 --- /dev/null +++ b/bsp/coreip-s54/README.md @@ -0,0 +1,11 @@ +The SiFive S54 Standard Core is a 64-bit embedded processor that is fully-compliant with the RISC-V ISA. It adds support for the F and D standard extensions, which provide the S54 with double-precision floating-point capabilities. + +The S54 is ideal for demanding applications such as avionics, signal processing, and industrial automation. + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV64IMAFDC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 255 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels -- cgit v1.2.3