From 0fe5ca97956cc15effd0c459a81c8caacbc80ac3 Mon Sep 17 00:00:00 2001
From: Bunnaroath Sou <bsou@sifive.com>
Date: Mon, 18 Mar 2019 12:58:11 -0700
Subject: Update Arty clock to reflects HW

---
 bsp/coreip-s76-arty/design.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'bsp/coreip-s76-arty/design.dts')

diff --git a/bsp/coreip-s76-arty/design.dts b/bsp/coreip-s76-arty/design.dts
index f43d9c5..736d909 100644
--- a/bsp/coreip-s76-arty/design.dts
+++ b/bsp/coreip-s76-arty/design.dts
@@ -29,7 +29,7 @@
 			reg = <0x0>;
 			riscv,isa = "rv64imafdc";
 			status = "okay";
-			timebase-frequency = <1000000>;
+			timebase-frequency = <65000000>;
                         hardware-exec-breakpoint-count = <4>;
 			L4: interrupt-controller {
 				#interrupt-cells = <1>;
-- 
cgit v1.2.1-18-gbd029