From 983a630b07f08af869adc78cb37bf634389519af Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Thu, 7 Mar 2019 11:28:06 -0800 Subject: Rename coreip-X to coreip-X-rtl Signed-off-by: Nathaniel Graff --- bsp/coreip-s76-rtl/README.md | 11 +++++++++++ 1 file changed, 11 insertions(+) create mode 100644 bsp/coreip-s76-rtl/README.md (limited to 'bsp/coreip-s76-rtl/README.md') diff --git a/bsp/coreip-s76-rtl/README.md b/bsp/coreip-s76-rtl/README.md new file mode 100644 index 0000000..9623a83 --- /dev/null +++ b/bsp/coreip-s76-rtl/README.md @@ -0,0 +1,11 @@ +The SiFive S76 Standard Core is a high-performance 64-bit embedded processor which is fully-compliant with the RISC-V ISA. + +The S76 is ideal for latency-sensitive applications in domains such as storage and networking that require 64-bit memory addressability (e.g. In-storage Compute, Edge Compute, 5G Modems, Object storage etc.) + +This core target is suitable with Verilog RTL for verification and running application software building on top of freedom-metal libraries. The target supports: + +- 1 hart with RV64IMAFDC core +- 4 hardware breakpoints +- Physical Memory Protection with 8 regions +- 16 local interrupts signal that can be connected to off core complex devices +- Up to 127 PLIC interrupt signals that can be connected to off core complex devices, with 7 priority levels -- cgit v1.2.1-18-gbd029