From b87018b8a5afa98a6f799527d9a4417290349a4a Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 21 May 2019 10:51:18 -0700 Subject: Modify BSP DTSs to use riscv,pmpregions property Signed-off-by: Nathaniel Graff --- bsp/coreip-u54mc-rtl/design.dts | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'bsp/coreip-u54mc-rtl/design.dts') diff --git a/bsp/coreip-u54mc-rtl/design.dts b/bsp/coreip-u54mc-rtl/design.dts index 27a3c94..beba177 100644 --- a/bsp/coreip-u54mc-rtl/design.dts +++ b/bsp/coreip-u54mc-rtl/design.dts @@ -18,6 +18,7 @@ next-level-cache = <&L33>; reg = <0x0>; riscv,isa = "rv64imac"; + riscv,pmpregions = <8>; sifive,dtim = <&L7>; sifive,itim = <&L6>; status = "okay"; @@ -46,6 +47,7 @@ next-level-cache = <&L33>; reg = <0x1>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L11>; status = "okay"; timebase-frequency = <1000000>; @@ -74,6 +76,7 @@ next-level-cache = <&L33>; reg = <0x2>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L15>; status = "okay"; timebase-frequency = <1000000>; @@ -102,6 +105,7 @@ next-level-cache = <&L33>; reg = <0x3>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L19>; status = "okay"; timebase-frequency = <1000000>; @@ -130,6 +134,7 @@ next-level-cache = <&L33>; reg = <0x4>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L23>; status = "okay"; timebase-frequency = <1000000>; @@ -150,10 +155,6 @@ #size-cells = <2>; compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L30: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; -- cgit v1.2.3 From 4bbcff4155b8203a02987226427adec036825c66 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Wed, 22 May 2019 13:43:01 -0700 Subject: Set the boot hart for u54mc to 1 Signed-off-by: Nathaniel Graff --- bsp/coreip-u54mc-rtl/design.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'bsp/coreip-u54mc-rtl/design.dts') diff --git a/bsp/coreip-u54mc-rtl/design.dts b/bsp/coreip-u54mc-rtl/design.dts index beba177..2982dd5 100644 --- a/bsp/coreip-u54mc-rtl/design.dts +++ b/bsp/coreip-u54mc-rtl/design.dts @@ -5,6 +5,9 @@ #size-cells = <2>; compatible = "SiFive,FU540G-dev", "fu540-dev", "sifive-dev"; model = "SiFive,FU540G"; + chosen { + metal,boothart = <&L13>; + }; L36: cpus { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3