From b87018b8a5afa98a6f799527d9a4417290349a4a Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 21 May 2019 10:51:18 -0700 Subject: Modify BSP DTSs to use riscv,pmpregions property Signed-off-by: Nathaniel Graff --- bsp/coreip-u54mc-rtl/design.dts | 9 +++++---- 1 file changed, 5 insertions(+), 4 deletions(-) (limited to 'bsp/coreip-u54mc-rtl') diff --git a/bsp/coreip-u54mc-rtl/design.dts b/bsp/coreip-u54mc-rtl/design.dts index 27a3c94..beba177 100644 --- a/bsp/coreip-u54mc-rtl/design.dts +++ b/bsp/coreip-u54mc-rtl/design.dts @@ -18,6 +18,7 @@ next-level-cache = <&L33>; reg = <0x0>; riscv,isa = "rv64imac"; + riscv,pmpregions = <8>; sifive,dtim = <&L7>; sifive,itim = <&L6>; status = "okay"; @@ -46,6 +47,7 @@ next-level-cache = <&L33>; reg = <0x1>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L11>; status = "okay"; timebase-frequency = <1000000>; @@ -74,6 +76,7 @@ next-level-cache = <&L33>; reg = <0x2>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L15>; status = "okay"; timebase-frequency = <1000000>; @@ -102,6 +105,7 @@ next-level-cache = <&L33>; reg = <0x3>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L19>; status = "okay"; timebase-frequency = <1000000>; @@ -130,6 +134,7 @@ next-level-cache = <&L33>; reg = <0x4>; riscv,isa = "rv64imafdc"; + riscv,pmpregions = <8>; sifive,itim = <&L23>; status = "okay"; timebase-frequency = <1000000>; @@ -150,10 +155,6 @@ #size-cells = <2>; compatible = "SiFive,FU540G-soc", "fu540-soc", "sifive-soc", "simple-bus"; ranges; - pmp: pmp@0 { - compatible = "riscv,pmp"; - regions = <8>; - }; L30: axi4-periph-port@20000000 { #address-cells = <2>; #size-cells = <2>; -- cgit v1.2.3 From c5dd42c68d030a356c85bb8d174296b4f2df615d Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Tue, 21 May 2019 10:55:10 -0700 Subject: Update BSPs Signed-off-by: Nathaniel Graff --- bsp/coreip-u54mc-rtl/metal-inline.h | 8 ++------ bsp/coreip-u54mc-rtl/metal-platform.h | 7 +------ bsp/coreip-u54mc-rtl/metal.default.lds | 2 +- bsp/coreip-u54mc-rtl/metal.h | 29 +++++++++++++++++++++++++---- bsp/coreip-u54mc-rtl/metal.ramrodata.lds | 2 +- bsp/coreip-u54mc-rtl/metal.scratchpad.lds | 2 +- bsp/coreip-u54mc-rtl/settings.mk | 2 +- 7 files changed, 32 insertions(+), 20 deletions(-) (limited to 'bsp/coreip-u54mc-rtl') diff --git a/bsp/coreip-u54mc-rtl/metal-inline.h b/bsp/coreip-u54mc-rtl/metal-inline.h index 58f8acc..62b9eb9 100644 --- a/bsp/coreip-u54mc-rtl/metal-inline.h +++ b/bsp/coreip-u54mc-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -29,6 +29,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); +extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); /* --------------------- sifive_plic0 ------------ */ @@ -235,11 +236,6 @@ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000 = { .init_done = 0, }; -/* From pmp@0 */ -struct metal_pmp __metal_dt_pmp_0 = { - .num_regions = METAL_RISCV_PMP_0_NUM_REGIONS, -}; - /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts = { .irc.vtable = &__metal_driver_vtable_sifive_global_external_interrupts0.global0_vtable, diff --git a/bsp/coreip-u54mc-rtl/metal-platform.h b/bsp/coreip-u54mc-rtl/metal-platform.h index 6df003f..0919ca3 100644 --- a/bsp/coreip-u54mc-rtl/metal-platform.h +++ b/bsp/coreip-u54mc-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef COREIP_U54MC_RTL__METAL_PLATFORM_H @@ -35,11 +35,6 @@ #define METAL_RISCV_PLIC0_THRESHOLD 2097152UL #define METAL_RISCV_PLIC0_CLAIM 2097156UL -/* From pmp@0 */ -#define METAL_RISCV_PMP_0_NUM_REGIONS 8UL - -#define METAL_RISCV_PMP - /* From cache_controller@2010000 */ #define METAL_SIFIVE_FU540_C000_L2_2010000_BASE_ADDRESS 33619968UL #define METAL_SIFIVE_FU540_C000_L2_0_BASE_ADDRESS 33619968UL diff --git a/bsp/coreip-u54mc-rtl/metal.default.lds b/bsp/coreip-u54mc-rtl/metal.default.lds index ea7c853..32ee163 100644 --- a/bsp/coreip-u54mc-rtl/metal.default.lds +++ b/bsp/coreip-u54mc-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-u54mc-rtl/metal.h b/bsp/coreip-u54mc-rtl/metal.h index dab7ff4..f60e70c 100644 --- a/bsp/coreip-u54mc-rtl/metal.h +++ b/bsp/coreip-u54mc-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -122,7 +122,7 @@ struct __metal_driver_riscv_cpu_intc __metal_dt_cpu_4_interrupt_controller; /* From interrupt_controller@c000000 */ struct __metal_driver_riscv_plic0 __metal_dt_interrupt_controller_c000000; -struct metal_pmp __metal_dt_pmp_0; +struct metal_pmp __metal_dt_pmp; /* From global_external_interrupts */ struct __metal_driver_sifive_global_external_interrupts0 __metal_dt_global_external_interrupts; @@ -293,6 +293,28 @@ static inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(s } } +static inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) { + return 8; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) { + return 8; + } + else { + return 0; + } +} + /* --------------------- sifive_plic0 ------------ */ @@ -912,8 +934,7 @@ struct __metal_driver_cpu *__metal_cpu_table[] = { #define __METAL_DT_INTERRUPT_CONTROLLER_C000000_HANDLE (&__metal_dt_interrupt_controller_c000000.controller) -/* From pmp@0 */ -#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp_0) +#define __METAL_DT_PMP_HANDLE (&__metal_dt_pmp) /* From global_external_interrupts */ #define __METAL_DT_SIFIVE_GLOBAL_EXINTR0_HANDLE (&__metal_dt_global_external_interrupts.irc) diff --git a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds index 2dca5ed..6a59904 100644 --- a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds +++ b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds index ea7c853..32ee163 100644 --- a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds +++ b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 20-05-2019 14-26-11 */ +/* [XXXXX] 21-05-2019 10-54-35 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk index e59f66a..4509247 100644 --- a/bsp/coreip-u54mc-rtl/settings.mk +++ b/bsp/coreip-u54mc-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 20-05-2019 14-26-11 # +# [XXXXX] 21-05-2019 10-54-35 # # ----------------------------------- # RISCV_ARCH=rv64imac -- cgit v1.2.3 From 4bbcff4155b8203a02987226427adec036825c66 Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Wed, 22 May 2019 13:43:01 -0700 Subject: Set the boot hart for u54mc to 1 Signed-off-by: Nathaniel Graff --- bsp/coreip-u54mc-rtl/design.dts | 3 +++ 1 file changed, 3 insertions(+) (limited to 'bsp/coreip-u54mc-rtl') diff --git a/bsp/coreip-u54mc-rtl/design.dts b/bsp/coreip-u54mc-rtl/design.dts index beba177..2982dd5 100644 --- a/bsp/coreip-u54mc-rtl/design.dts +++ b/bsp/coreip-u54mc-rtl/design.dts @@ -5,6 +5,9 @@ #size-cells = <2>; compatible = "SiFive,FU540G-dev", "fu540-dev", "sifive-dev"; model = "SiFive,FU540G"; + chosen { + metal,boothart = <&L13>; + }; L36: cpus { #address-cells = <1>; #size-cells = <0>; -- cgit v1.2.3 From 2cc2f5e07ad2bfdefc03d443a533d1c5455c283f Mon Sep 17 00:00:00 2001 From: Nathaniel Graff Date: Wed, 22 May 2019 13:39:43 -0700 Subject: Update BSPs Signed-off-by: Nathaniel Graff --- bsp/coreip-u54mc-rtl/metal-inline.h | 3 ++- bsp/coreip-u54mc-rtl/metal-platform.h | 2 +- bsp/coreip-u54mc-rtl/metal.default.lds | 3 ++- bsp/coreip-u54mc-rtl/metal.h | 24 +++++++++++++++++++++++- bsp/coreip-u54mc-rtl/metal.ramrodata.lds | 3 ++- bsp/coreip-u54mc-rtl/metal.scratchpad.lds | 3 ++- bsp/coreip-u54mc-rtl/settings.mk | 3 ++- 7 files changed, 34 insertions(+), 7 deletions(-) (limited to 'bsp/coreip-u54mc-rtl') diff --git a/bsp/coreip-u54mc-rtl/metal-inline.h b/bsp/coreip-u54mc-rtl/metal-inline.h index 62b9eb9..34e4d33 100644 --- a/bsp/coreip-u54mc-rtl/metal-inline.h +++ b/bsp/coreip-u54mc-rtl/metal-inline.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 21-05-2019 10-54-35 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -27,6 +27,7 @@ extern inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +extern inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu); extern inline struct metal_interrupt * __metal_driver_cpu_interrupt_controller(struct metal_cpu *cpu); extern inline int __metal_driver_cpu_num_pmp_regions(struct metal_cpu *cpu); diff --git a/bsp/coreip-u54mc-rtl/metal-platform.h b/bsp/coreip-u54mc-rtl/metal-platform.h index 0919ca3..7045d23 100644 --- a/bsp/coreip-u54mc-rtl/metal-platform.h +++ b/bsp/coreip-u54mc-rtl/metal-platform.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 21-05-2019 10-54-35 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef COREIP_U54MC_RTL__METAL_PLATFORM_H diff --git a/bsp/coreip-u54mc-rtl/metal.default.lds b/bsp/coreip-u54mc-rtl/metal.default.lds index 32ee163..a95cc07 100644 --- a/bsp/coreip-u54mc-rtl/metal.default.lds +++ b/bsp/coreip-u54mc-rtl/metal.default.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 21-05-2019 10-54-35 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 1); .init : diff --git a/bsp/coreip-u54mc-rtl/metal.h b/bsp/coreip-u54mc-rtl/metal.h index f60e70c..417332f 100644 --- a/bsp/coreip-u54mc-rtl/metal.h +++ b/bsp/coreip-u54mc-rtl/metal.h @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 21-05-2019 10-54-35 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ #ifndef ASSEMBLY @@ -249,6 +249,28 @@ static inline int __metal_driver_sifive_clint0_interrupt_lines(struct metal_inte /* --------------------- cpu ------------ */ +static inline int __metal_driver_cpu_hartid(struct metal_cpu *cpu) +{ + if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { + return 0; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_1) { + return 1; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_2) { + return 2; + } + else if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_3) { + return 3; + } + else { + return -1; + } +} + static inline int __metal_driver_cpu_timebase(struct metal_cpu *cpu) { if ((uintptr_t)cpu == (uintptr_t)&__metal_dt_cpu_0) { diff --git a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds index 6a59904..b5f35f7 100644 --- a/bsp/coreip-u54mc-rtl/metal.ramrodata.lds +++ b/bsp/coreip-u54mc-rtl/metal.ramrodata.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 21-05-2019 10-54-35 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 1); .init : diff --git a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds index 32ee163..a95cc07 100644 --- a/bsp/coreip-u54mc-rtl/metal.scratchpad.lds +++ b/bsp/coreip-u54mc-rtl/metal.scratchpad.lds @@ -1,7 +1,7 @@ /* Copyright 2019 SiFive, Inc */ /* SPDX-License-Identifier: Apache-2.0 */ /* ----------------------------------- */ -/* [XXXXX] 21-05-2019 10-54-35 */ +/* [XXXXX] 23-05-2019 13-29-49 */ /* ----------------------------------- */ OUTPUT_ARCH("riscv") @@ -28,6 +28,7 @@ SECTIONS __stack_size = DEFINED(__stack_size) ? __stack_size : 0x400; PROVIDE(__stack_size = __stack_size); __heap_size = DEFINED(__heap_size) ? __heap_size : 0x400; + PROVIDE(__metal_boot_hart = 1); .init : diff --git a/bsp/coreip-u54mc-rtl/settings.mk b/bsp/coreip-u54mc-rtl/settings.mk index 4509247..ae9e038 100644 --- a/bsp/coreip-u54mc-rtl/settings.mk +++ b/bsp/coreip-u54mc-rtl/settings.mk @@ -1,7 +1,7 @@ # Copyright 2019 SiFive, Inc # # SPDX-License-Identifier: Apache-2.0 # # ----------------------------------- # -# [XXXXX] 21-05-2019 10-54-35 # +# [XXXXX] 23-05-2019 13-29-49 # # ----------------------------------- # RISCV_ARCH=rv64imac @@ -11,3 +11,4 @@ RISCV_CMODEL=medany COREIP_MEM_WIDTH=128 TARGET_TAGS=rtl +TARGET_DHRY_ITERS=2000 -- cgit v1.2.3