From abbf5a2ef4b46218a1b24ef6afd6cf7b35a87e55 Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Mon, 2 Jul 2018 00:40:06 -0500
Subject: e2 and clic start

---
 bsp/env/common.mk                          |   2 +-
 bsp/env/coreip-e2-arty/init.c              |  95 +++++++++++++++++
 bsp/env/coreip-e2-arty/openocd.cfg         |   1 +
 bsp/env/coreip-e2-arty/platform.h          |  92 +++++++++++++++++
 bsp/env/coreip-e2-arty/settings.mk         |   1 +
 bsp/env/coreip-e2-arty/tim-split.lds       | 157 ++++++++++++++++++++++++++++
 bsp/env/coreip-e2-arty/tim.lds             | 161 +++++++++++++++++++++++++++++
 bsp/env/coreplexip-e21-arty/dhrystone.lds  |   1 -
 bsp/env/coreplexip-e21-arty/flash.lds      |   1 -
 bsp/env/coreplexip-e21-arty/init.c         |   1 -
 bsp/env/coreplexip-e21-arty/openocd.cfg    |   1 -
 bsp/env/coreplexip-e21-arty/platform.h     |   1 -
 bsp/env/coreplexip-e21-arty/scratchpad.lds |   1 -
 bsp/env/coreplexip-e21-arty/settings.mk    |   1 -
 14 files changed, 508 insertions(+), 8 deletions(-)
 create mode 100644 bsp/env/coreip-e2-arty/init.c
 create mode 120000 bsp/env/coreip-e2-arty/openocd.cfg
 create mode 100644 bsp/env/coreip-e2-arty/platform.h
 create mode 120000 bsp/env/coreip-e2-arty/settings.mk
 create mode 100644 bsp/env/coreip-e2-arty/tim-split.lds
 create mode 100644 bsp/env/coreip-e2-arty/tim.lds
 delete mode 120000 bsp/env/coreplexip-e21-arty/dhrystone.lds
 delete mode 120000 bsp/env/coreplexip-e21-arty/flash.lds
 delete mode 120000 bsp/env/coreplexip-e21-arty/init.c
 delete mode 120000 bsp/env/coreplexip-e21-arty/openocd.cfg
 delete mode 120000 bsp/env/coreplexip-e21-arty/platform.h
 delete mode 120000 bsp/env/coreplexip-e21-arty/scratchpad.lds
 delete mode 120000 bsp/env/coreplexip-e21-arty/settings.mk

(limited to 'bsp/env')

diff --git a/bsp/env/common.mk b/bsp/env/common.mk
index 4566b80..74939a5 100644
--- a/bsp/env/common.mk
+++ b/bsp/env/common.mk
@@ -25,7 +25,7 @@ INCLUDES += -I$(PLATFORM_DIR)
 TOOL_DIR = $(BSP_BASE)/../toolchain/bin
 
 LDFLAGS += -T $(LINKER_SCRIPT) -nostartfiles
-LDFLAGS += -L$(ENV_DIR)
+LDFLAGS += -L$(ENV_DIR) --specs=nano.specs
 
 ASM_OBJS := $(ASM_SRCS:.S=.o)
 C_OBJS := $(C_SRCS:.c=.o)
diff --git a/bsp/env/coreip-e2-arty/init.c b/bsp/env/coreip-e2-arty/init.c
new file mode 100644
index 0000000..aaf213c
--- /dev/null
+++ b/bsp/env/coreip-e2-arty/init.c
@@ -0,0 +1,95 @@
+//See LICENSE for license details.
+#include <stdint.h>
+#include <stdio.h>
+#include <unistd.h>
+
+#include "platform.h"
+#include "encoding.h"
+
+#define CPU_FREQ 32000000
+#define XSTR(x) #x
+#define STR(x) XSTR(x)
+
+extern int main(int argc, char** argv);
+
+unsigned long get_cpu_freq()
+{
+  return CPU_FREQ;
+}
+
+unsigned long get_timer_freq()
+{
+  return get_cpu_freq();
+}
+
+uint64_t get_timer_value()
+{
+#if __riscv_xlen == 32
+  while (1) {
+    uint32_t hi = read_csr(mcycleh);
+    uint32_t lo = read_csr(mcycle);
+    if (hi == read_csr(mcycleh))
+      return ((uint64_t)hi << 32) | lo;
+  }
+#else
+  return read_csr(mcycle);
+#endif
+}
+
+static void uart_init(size_t baud_rate)
+{
+  UART0_REG(UART_REG_DIV) = (get_cpu_freq() ) / baud_rate - 1;
+  UART0_REG(UART_REG_TXCTRL) |= UART_TXEN;
+}
+
+
+typedef void (*interrupt_function_ptr_t) (void);
+interrupt_function_ptr_t localISR[CLIC_NUM_INTERRUPTS] __attribute__((aligned(64)));
+
+void trap_entry(void) __attribute__((interrupt("SiFive-CLIC-preemptible"), aligned(64)));
+void trap_entry(void)
+{
+  unsigned long mcause = read_csr(mcause);
+  unsigned long mepc = read_csr(mepc);
+  if (mcause & MCAUSE_INT)  {
+    localISR[mcause & MCAUSE_CAUSE] ();
+  } else {
+    while(1);
+  }
+}
+
+#ifdef CLIC_DIRECT
+#else
+void default_handler(void)__attribute__((interrupt("SiFive-CLIC-preemptible")));;
+#endif
+void default_handler(void)
+{
+  puts("default handler\n");
+  while(1);
+}
+
+void _init()
+{
+#ifndef NO_INIT
+  uart_init(115200);
+
+  puts("core freq at " STR(CPU_FREQ) " Hz\n");
+
+//initialize vector table
+  for(int i=0;i++;i<CLIC_NUM_INTERRUPTS)  {
+    localISR[i] = &default_handler;
+  }
+  write_csr(mtvt, localISR);
+
+#ifdef CLIC_DIRECT
+  write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC));
+#else
+  write_csr(mtvec, ((unsigned long)&trap_entry | MTVEC_CLIC_VECT));
+#endif
+
+#endif
+}
+
+void _fini()
+{
+}
diff --git a/bsp/env/coreip-e2-arty/openocd.cfg b/bsp/env/coreip-e2-arty/openocd.cfg
new file mode 120000
index 0000000..2f4de8d
--- /dev/null
+++ b/bsp/env/coreip-e2-arty/openocd.cfg
@@ -0,0 +1 @@
+../coreplexip-e31-arty/openocd.cfg
\ No newline at end of file
diff --git a/bsp/env/coreip-e2-arty/platform.h b/bsp/env/coreip-e2-arty/platform.h
new file mode 100644
index 0000000..8ee0a83
--- /dev/null
+++ b/bsp/env/coreip-e2-arty/platform.h
@@ -0,0 +1,92 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_PLATFORM_H
+#define _SIFIVE_PLATFORM_H
+
+// Some things missing from the official encoding.h
+
+#if __riscv_xlen == 32
+#define MCAUSE_INT         0x80000000UL
+#define MCAUSE_CAUSE       0x000003FFUL
+#else
+#define MCAUSE_INT         0x8000000000000000UL
+#define MCAUSE_CAUSE       0x00000000000003FFUL
+#endif
+
+#define MTVEC_DIRECT       0X00
+#define MTVEC_VECTORED     0x01
+#define MTVEC_CLIC         0x02
+#define MTVEC_CLIC_VECT    0X03
+
+
+#include "sifive/const.h"
+#include "sifive/devices/gpio.h"
+#include "sifive/devices/clic.h"
+#include "sifive/devices/pwm.h"
+#include "sifive/devices/spi.h"
+#include "sifive/devices/uart.h"
+
+/****************************************************************************
+ * Platform definitions
+ *****************************************************************************/
+
+// Memory map
+#define CLINT_CTRL_ADDR _AC(0x02000000,UL)
+#define CLIC_HART0_ADDR _AC(0x02800000, UL)
+#define GPIO_CTRL_ADDR _AC(0x20002000,UL)
+#define PWM0_CTRL_ADDR _AC(0x20005000,UL)
+#define RAM_MEM_ADDR _AC(0x80000000,UL)
+#define RAM_MEM_SIZE _AC(0x10000,UL)
+#define SPI0_CTRL_ADDR _AC(0x20004000,UL)
+#define SPI0_MEM_ADDR _AC(0x40000000,UL)
+#define SPI0_MEM_SIZE _AC(0x20000000,UL)
+#define TESTBENCH_MEM_ADDR _AC(0x20000000,UL)
+#define TESTBENCH_MEM_SIZE _AC(0x10000000,UL)
+//#define TRAPVEC_TABLE_CTRL_ADDR _AC(0x00001010,UL)
+#define UART0_CTRL_ADDR _AC(0x20000000,UL)
+
+// IOF masks
+
+// Interrupt numbers
+#define RESERVED_INT_BASE 0
+#define UART0_INT_BASE 1
+#define EXTERNAL_INT_BASE 2
+#define SPI0_INT_BASE 6
+#define GPIO_INT_BASE 7
+#define PWM0_INT_BASE 23
+
+// Helper functions
+#define _REG64(p, i) (*(volatile uint64_t *)((p) + (i)))
+#define _REG32(p, i) (*(volatile uint32_t *)((p) + (i)))
+#define _REG16(p, i) (*(volatile uint16_t *)((p) + (i)))
+#define SET_BITS(reg, mask, value) if ((value) == 0) { (reg) &= ~(mask); } else { (reg) |= (mask); }
+#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
+#define CLIC0_REG(offset) _REG32(CLIC_HART0_ADDR, offset)
+#define CLIC0_REG8(offset)   (*(volatile uint8_t *)((CLIC_HART0_ADDR) + (offset)))
+#define GPIO_REG(offset) _REG32(GPIO_CTRL_ADDR, offset)
+#define PWM0_REG(offset) _REG32(PWM0_CTRL_ADDR, offset)
+#define SPI0_REG(offset) _REG32(SPI0_CTRL_ADDR, offset)
+#define UART0_REG(offset) _REG32(UART0_CTRL_ADDR, offset)
+#define CLINT_REG(offset) _REG32(CLINT_CTRL_ADDR, offset)
+#define CLIC0_REG64(offset) _REG64(CLIC_HART0_ADDR, offset)
+#define GPIO_REG64(offset) _REG64(GPIO_CTRL_ADDR, offset)
+#define PWM0_REG64(offset) _REG64(PWM0_CTRL_ADDR, offset)
+#define SPI0_REG64(offset) _REG64(SPI0_CTRL_ADDR, offset)
+#define UART0_REG64(offset) _REG64(UART0_CTRL_ADDR, offset)
+
+// Misc
+
+#define NUM_GPIO 16
+
+#define CLIC_NUM_INTERRUPTS 28 + 16
+#define CLIC_NUM_CONFIG_BITS 4 //2 for E20
+
+#define HAS_BOARD_BUTTONS
+
+#include "coreplexip-arty.h"
+
+unsigned long get_cpu_freq(void);
+unsigned long get_timer_freq(void);
+uint64_t get_timer_value(void);
+
+#endif /* _SIFIVE_PLATFORM_H */
diff --git a/bsp/env/coreip-e2-arty/settings.mk b/bsp/env/coreip-e2-arty/settings.mk
new file mode 120000
index 0000000..2b2a962
--- /dev/null
+++ b/bsp/env/coreip-e2-arty/settings.mk
@@ -0,0 +1 @@
+../coreplexip-e31-arty/settings.mk
\ No newline at end of file
diff --git a/bsp/env/coreip-e2-arty/tim-split.lds b/bsp/env/coreip-e2-arty/tim-split.lds
new file mode 100644
index 0000000..eab4bd3
--- /dev/null
+++ b/bsp/env/coreip-e2-arty/tim-split.lds
@@ -0,0 +1,157 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  flash (rxai!w) : ORIGIN = 0x80008000, LENGTH = 32K
+  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 32K
+}
+
+PHDRS
+{
+  flash PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
+
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash :flash
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash :flash
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash :flash
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash :flash
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash :flash
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash :flash
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash :flash
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash :flash
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash :flash
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash :ram_init
+
+  .data          :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+}
diff --git a/bsp/env/coreip-e2-arty/tim.lds b/bsp/env/coreip-e2-arty/tim.lds
new file mode 100644
index 0000000..7dfb36b
--- /dev/null
+++ b/bsp/env/coreip-e2-arty/tim.lds
@@ -0,0 +1,161 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K
+}
+
+PHDRS
+{
+  ram PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 1K;
+
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >ram AT>ram :ram
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >ram AT>ram :ram
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >ram AT>ram :ram
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >ram AT>ram :ram
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >ram AT>ram :ram
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >ram AT>ram :ram
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >ram AT>ram :ram
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >ram AT>ram :ram
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >ram AT>ram :ram
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >ram AT>ram :ram
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>ram :ram_init
+
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>ram :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack :
+  {
+    . = ALIGN(8);
+    . += __stack_size;
+    PROVIDE( _sp = . );
+    PROVIDE( _heap_end = . );
+  } >ram AT>ram :ram
+}
diff --git a/bsp/env/coreplexip-e21-arty/dhrystone.lds b/bsp/env/coreplexip-e21-arty/dhrystone.lds
deleted file mode 120000
index 8459e13..0000000
--- a/bsp/env/coreplexip-e21-arty/dhrystone.lds
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/dhrystone.lds
\ No newline at end of file
diff --git a/bsp/env/coreplexip-e21-arty/flash.lds b/bsp/env/coreplexip-e21-arty/flash.lds
deleted file mode 120000
index 54c1026..0000000
--- a/bsp/env/coreplexip-e21-arty/flash.lds
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/flash.lds
\ No newline at end of file
diff --git a/bsp/env/coreplexip-e21-arty/init.c b/bsp/env/coreplexip-e21-arty/init.c
deleted file mode 120000
index de048a9..0000000
--- a/bsp/env/coreplexip-e21-arty/init.c
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/init.c
\ No newline at end of file
diff --git a/bsp/env/coreplexip-e21-arty/openocd.cfg b/bsp/env/coreplexip-e21-arty/openocd.cfg
deleted file mode 120000
index 2f4de8d..0000000
--- a/bsp/env/coreplexip-e21-arty/openocd.cfg
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/openocd.cfg
\ No newline at end of file
diff --git a/bsp/env/coreplexip-e21-arty/platform.h b/bsp/env/coreplexip-e21-arty/platform.h
deleted file mode 120000
index 311ca36..0000000
--- a/bsp/env/coreplexip-e21-arty/platform.h
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/platform.h
\ No newline at end of file
diff --git a/bsp/env/coreplexip-e21-arty/scratchpad.lds b/bsp/env/coreplexip-e21-arty/scratchpad.lds
deleted file mode 120000
index 7fbe10a..0000000
--- a/bsp/env/coreplexip-e21-arty/scratchpad.lds
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/scratchpad.lds
\ No newline at end of file
diff --git a/bsp/env/coreplexip-e21-arty/settings.mk b/bsp/env/coreplexip-e21-arty/settings.mk
deleted file mode 120000
index 2b2a962..0000000
--- a/bsp/env/coreplexip-e21-arty/settings.mk
+++ /dev/null
@@ -1 +0,0 @@
-../coreplexip-e31-arty/settings.mk
\ No newline at end of file
-- 
cgit v1.2.1-18-gbd029


From 833e3fadf745dfdec6c8208f6c3b2ffd7b5a6f7f Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Mon, 2 Jul 2018 01:48:36 -0500
Subject: dont use pre-empt with buttons

---
 bsp/env/coreip-e2-arty/init.c | 13 ++++++++-----
 1 file changed, 8 insertions(+), 5 deletions(-)

(limited to 'bsp/env')

diff --git a/bsp/env/coreip-e2-arty/init.c b/bsp/env/coreip-e2-arty/init.c
index aaf213c..3a4c77c 100644
--- a/bsp/env/coreip-e2-arty/init.c
+++ b/bsp/env/coreip-e2-arty/init.c
@@ -46,7 +46,8 @@ static void uart_init(size_t baud_rate)
 typedef void (*interrupt_function_ptr_t) (void);
 interrupt_function_ptr_t localISR[CLIC_NUM_INTERRUPTS] __attribute__((aligned(64)));
 
-void trap_entry(void) __attribute__((interrupt("SiFive-CLIC-preemptible"), aligned(64)));
+
+void trap_entry(void) __attribute__((interrupt, aligned(64)));
 void trap_entry(void)
 {
   unsigned long mcause = read_csr(mcause);
@@ -54,13 +55,13 @@ void trap_entry(void)
   if (mcause & MCAUSE_INT)  {
     localISR[mcause & MCAUSE_CAUSE] ();
   } else {
-    while(1);
+    while(1); 
   }
 }
 
 #ifdef CLIC_DIRECT
 #else
-void default_handler(void)__attribute__((interrupt("SiFive-CLIC-preemptible")));;
+void default_handler(void)__attribute__((interrupt));;
 #endif
 void default_handler(void)
 {
@@ -76,9 +77,11 @@ void _init()
   puts("core freq at " STR(CPU_FREQ) " Hz\n");
 
 //initialize vector table
-  for(int i=0;i++;i<CLIC_NUM_INTERRUPTS)  {
-    localISR[i] = &default_handler;
+  int i=0;
+  while(i<CLIC_NUM_INTERRUPTS)	{
+    localISR[i++] = default_handler;
   }
+  
   write_csr(mtvt, localISR);
 
 #ifdef CLIC_DIRECT
-- 
cgit v1.2.1-18-gbd029


From 835b33318a3b350051ef153d382a5980efe19ed6 Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Mon, 2 Jul 2018 16:04:45 -0500
Subject: update description

---
 bsp/env/coreip-e2-arty/platform.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'bsp/env')

diff --git a/bsp/env/coreip-e2-arty/platform.h b/bsp/env/coreip-e2-arty/platform.h
index 8ee0a83..6bf2121 100644
--- a/bsp/env/coreip-e2-arty/platform.h
+++ b/bsp/env/coreip-e2-arty/platform.h
@@ -79,7 +79,7 @@
 #define NUM_GPIO 16
 
 #define CLIC_NUM_INTERRUPTS 28 + 16
-#define CLIC_NUM_CONFIG_BITS 4 //2 for E20
+#define CLIC_CONFIG_BITS 0x1E //2 for E20
 
 #define HAS_BOARD_BUTTONS
 
-- 
cgit v1.2.1-18-gbd029


From 9d58b2120c5a9b9dbc95c0ea90b16280e36dc9ca Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Mon, 2 Jul 2018 22:48:21 -0500
Subject: short msi handler

---
 bsp/env/coreip-e2-arty/platform.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'bsp/env')

diff --git a/bsp/env/coreip-e2-arty/platform.h b/bsp/env/coreip-e2-arty/platform.h
index 6bf2121..305726d 100644
--- a/bsp/env/coreip-e2-arty/platform.h
+++ b/bsp/env/coreip-e2-arty/platform.h
@@ -32,7 +32,7 @@
 
 // Memory map
 #define CLINT_CTRL_ADDR _AC(0x02000000,UL)
-#define CLIC_HART0_ADDR _AC(0x02800000, UL)
+#define CLIC_HART0_ADDR _AC(0x02800000,UL)
 #define GPIO_CTRL_ADDR _AC(0x20002000,UL)
 #define PWM0_CTRL_ADDR _AC(0x20005000,UL)
 #define RAM_MEM_ADDR _AC(0x80000000,UL)
-- 
cgit v1.2.1-18-gbd029


From 962b23a3797ba659577056ed3fc57c2d0a77df62 Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Wed, 4 Jul 2018 18:48:19 -0500
Subject: clic driver level and priority functions

---
 bsp/env/coreip-e2-arty/platform.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'bsp/env')

diff --git a/bsp/env/coreip-e2-arty/platform.h b/bsp/env/coreip-e2-arty/platform.h
index 305726d..ba06160 100644
--- a/bsp/env/coreip-e2-arty/platform.h
+++ b/bsp/env/coreip-e2-arty/platform.h
@@ -79,7 +79,7 @@
 #define NUM_GPIO 16
 
 #define CLIC_NUM_INTERRUPTS 28 + 16
-#define CLIC_CONFIG_BITS 0x1E //2 for E20
+#define CLIC_CONFIG_BITS 4
 
 #define HAS_BOARD_BUTTONS
 
-- 
cgit v1.2.1-18-gbd029


From c17273a65d0d2928217d587688f3fe2bea2406e8 Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Thu, 5 Jul 2018 22:32:56 -0500
Subject: support the E20

---
 bsp/env/coreip-e2-arty/platform.h | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

(limited to 'bsp/env')

diff --git a/bsp/env/coreip-e2-arty/platform.h b/bsp/env/coreip-e2-arty/platform.h
index ba06160..9ae9864 100644
--- a/bsp/env/coreip-e2-arty/platform.h
+++ b/bsp/env/coreip-e2-arty/platform.h
@@ -79,7 +79,12 @@
 #define NUM_GPIO 16
 
 #define CLIC_NUM_INTERRUPTS 28 + 16
-#define CLIC_CONFIG_BITS 4
+
+#ifdef E20
+   #define CLIC_CONFIG_BITS 2
+#else
+   #define CLIC_CONFIG_BITS 4
+#endif
 
 #define HAS_BOARD_BUTTONS
 
-- 
cgit v1.2.1-18-gbd029


From 6cebe81ad76bd44d71297b5ec19fef0b9a01817f Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Sun, 8 Jul 2018 18:02:20 -0500
Subject: FS projects

---
 bsp/env/coreip-e2-arty/flash.lds | 161 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 161 insertions(+)
 create mode 100644 bsp/env/coreip-e2-arty/flash.lds

(limited to 'bsp/env')

diff --git a/bsp/env/coreip-e2-arty/flash.lds b/bsp/env/coreip-e2-arty/flash.lds
new file mode 100644
index 0000000..2d5eb01
--- /dev/null
+++ b/bsp/env/coreip-e2-arty/flash.lds
@@ -0,0 +1,161 @@
+OUTPUT_ARCH( "riscv" )
+
+ENTRY( _start )
+
+MEMORY
+{
+  flash (rxai!w) : ORIGIN = 0x40400000, LENGTH = 512M
+  ram (wxa!ri) : ORIGIN = 0x80000000, LENGTH = 64K
+}
+
+PHDRS
+{
+  flash PT_LOAD;
+  ram_init PT_LOAD;
+  ram PT_NULL;
+}
+
+SECTIONS
+{
+  __stack_size = DEFINED(__stack_size) ? __stack_size : 2K;
+
+  .init           :
+  {
+    KEEP (*(SORT_NONE(.init)))
+  } >flash AT>flash :flash
+
+  .text           :
+  {
+    *(.text.unlikely .text.unlikely.*)
+    *(.text.startup .text.startup.*)
+    *(.text .text.*)
+    *(.gnu.linkonce.t.*)
+  } >flash AT>flash :flash
+
+  .fini           :
+  {
+    KEEP (*(SORT_NONE(.fini)))
+  } >flash AT>flash :flash
+
+  PROVIDE (__etext = .);
+  PROVIDE (_etext = .);
+  PROVIDE (etext = .);
+
+  .rodata         :
+  {
+    *(.rdata)
+    *(.rodata .rodata.*)
+    *(.gnu.linkonce.r.*)
+  } >flash AT>flash :flash
+
+  . = ALIGN(4);
+
+  .preinit_array  :
+  {
+    PROVIDE_HIDDEN (__preinit_array_start = .);
+    KEEP (*(.preinit_array))
+    PROVIDE_HIDDEN (__preinit_array_end = .);
+  } >flash AT>flash :flash
+
+  .init_array     :
+  {
+    PROVIDE_HIDDEN (__init_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.init_array.*) SORT_BY_INIT_PRIORITY(.ctors.*)))
+    KEEP (*(.init_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .ctors))
+    PROVIDE_HIDDEN (__init_array_end = .);
+  } >flash AT>flash :flash
+
+  .fini_array     :
+  {
+    PROVIDE_HIDDEN (__fini_array_start = .);
+    KEEP (*(SORT_BY_INIT_PRIORITY(.fini_array.*) SORT_BY_INIT_PRIORITY(.dtors.*)))
+    KEEP (*(.fini_array EXCLUDE_FILE (*crtbegin.o *crtbegin?.o *crtend.o *crtend?.o ) .dtors))
+    PROVIDE_HIDDEN (__fini_array_end = .);
+  } >flash AT>flash :flash
+
+  .ctors          :
+  {
+    /* gcc uses crtbegin.o to find the start of
+       the constructors, so we make sure it is
+       first.  Because this is a wildcard, it
+       doesn't matter if the user does not
+       actually link against crtbegin.o; the
+       linker won't look for a file to match a
+       wildcard.  The wildcard also means that it
+       doesn't matter which directory crtbegin.o
+       is in.  */
+    KEEP (*crtbegin.o(.ctors))
+    KEEP (*crtbegin?.o(.ctors))
+    /* We don't want to include the .ctor section from
+       the crtend.o file until after the sorted ctors.
+       The .ctor section from the crtend file contains the
+       end of ctors marker and it must be last */
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .ctors))
+    KEEP (*(SORT(.ctors.*)))
+    KEEP (*(.ctors))
+  } >flash AT>flash :flash
+
+  .dtors          :
+  {
+    KEEP (*crtbegin.o(.dtors))
+    KEEP (*crtbegin?.o(.dtors))
+    KEEP (*(EXCLUDE_FILE (*crtend.o *crtend?.o ) .dtors))
+    KEEP (*(SORT(.dtors.*)))
+    KEEP (*(.dtors))
+  } >flash AT>flash :flash
+
+  .lalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data_lma = . );
+  } >flash AT>flash :flash
+
+  .dalign         :
+  {
+    . = ALIGN(4);
+    PROVIDE( _data = . );
+  } >ram AT>flash :ram_init
+
+  .data          :
+  {
+    *(.data .data.*)
+    *(.gnu.linkonce.d.*)
+    . = ALIGN(8);
+    PROVIDE( __global_pointer$ = . + 0x800 );
+    *(.sdata .sdata.*)
+    *(.gnu.linkonce.s.*)
+    . = ALIGN(8);
+    *(.srodata.cst16)
+    *(.srodata.cst8)
+    *(.srodata.cst4)
+    *(.srodata.cst2)
+    *(.srodata .srodata.*)
+  } >ram AT>flash :ram_init
+
+  . = ALIGN(4);
+  PROVIDE( _edata = . );
+  PROVIDE( edata = . );
+
+  PROVIDE( _fbss = . );
+  PROVIDE( __bss_start = . );
+  .bss            :
+  {
+    *(.sbss*)
+    *(.gnu.linkonce.sb.*)
+    *(.bss .bss.*)
+    *(.gnu.linkonce.b.*)
+    *(COMMON)
+    . = ALIGN(4);
+  } >ram AT>ram :ram
+
+  . = ALIGN(8);
+  PROVIDE( _end = . );
+  PROVIDE( end = . );
+
+  .stack ORIGIN(ram) + LENGTH(ram) - __stack_size :
+  {
+    PROVIDE( _heap_end = . );
+    . = __stack_size;
+    PROVIDE( _sp = . );
+  } >ram AT>ram :ram
+}
-- 
cgit v1.2.1-18-gbd029


From 90968cafb22d81e01a6fd05055df3922215b88a9 Mon Sep 17 00:00:00 2001
From: Drew Barbier <dbarbi1@gmail.com>
Date: Sun, 8 Jul 2018 18:03:30 -0500
Subject: support clint only projects

---
 bsp/env/coreip-e2-arty/platform.h | 1 +
 1 file changed, 1 insertion(+)

(limited to 'bsp/env')

diff --git a/bsp/env/coreip-e2-arty/platform.h b/bsp/env/coreip-e2-arty/platform.h
index 9ae9864..0ce0484 100644
--- a/bsp/env/coreip-e2-arty/platform.h
+++ b/bsp/env/coreip-e2-arty/platform.h
@@ -21,6 +21,7 @@
 
 #include "sifive/const.h"
 #include "sifive/devices/gpio.h"
+#include "sifive/devices/clint.h"
 #include "sifive/devices/clic.h"
 #include "sifive/devices/pwm.h"
 #include "sifive/devices/spi.h"
-- 
cgit v1.2.1-18-gbd029